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DC Field | Value | Language |
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dc.contributor.author | SINGH, YASHPAL | - |
dc.date.accessioned | 2011-01-05T11:24:50Z | - |
dc.date.available | 2011-01-05T11:24:50Z | - |
dc.date.issued | 2010-09-17 | - |
dc.identifier.uri | http://dspace.dtu.ac.in:8080/jspui/handle/repository/701 | - |
dc.description | ME THESIS | en_US |
dc.description.abstract | The growth of analog IC design has been impeded by the process technologies which are mostly optimized for digital applications only. With the evolution of submicron technologies such as 0.18 micron and 0.13 micron, the supply voltages have been reduced to 1.8 Volts and lower. This makes it difficult to design a voltage mode CMOS circuits with high linearity and wide dynamic range. Recently, current mode circuits have become a viable alternative for future applications because of their inherent advantages over voltage mode circuits. The System on Chip (SoC) technology is highly on demand for digital signal processing applications and wireless systems where it has the ability to provide high speed together with the minimum hardware. In SoC designs, analog and digital building blocks are generally integrated at the same chip. In this case, there should be some interfaces between them. Analog to Digital Converters (ADCs) are the most commonly used mixed-signal modules which tr... | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartofseries | TD662;78 | - |
dc.subject | ANALOG | en_US |
dc.subject | DIGITAL CONVERTER | en_US |
dc.title | REALIZATION OF CURRENT MODE AREA SPEED EFFICIENT ANALOG TO DIGITALCONVERTER | en_US |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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Chap+1y.pdf | 6.17 MB | Adobe PDF | View/Open | |
CERTIFICATE1.pdf | 752.4 kB | Adobe PDF | View/Open |
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