SRAM DESIGN FOR THROUGH PUT ENHANCEMENT

Abstract

The rapid growth of data-intensive computing has increased the performance pressure on memory systems. In conventional processor–memory organizations, a significant fraction of energy and latency is consumed in transferring data between memory and logic units, even when the required operation is simple. Static random-access memory (SRAM) remains a key on-chip memory technology because of its high access speed, compatibility with standard CMOS processes, and widespread use in cache memories, register files, embedded bu!ers, and local storage blocks. However, SRAM design becomes increasingly di”cult under supply-voltage scaling, process-induced variation, bit-line loading, sensing delay, and energy constraints. These challenges become even more important when SRAM is extended from conventional storage to SRAM-based in-memory computing (SRAM-IMC), where the memory array is also used to perform local computation. SRAM-IMC o!ers a promising route to reduce repeated data movement by allowing selected logic operations to be performed within, or close to, the SRAM array. In this context, throughput enhancement cannot be treated as only a cell-level or macro-level problem. It requires coordinated design of the sensing path, bit-cell, compute macro, and array organization. The present research work therefore focuses on SRAM design for throughput enhancement using a circuit-to-array design approach. This thesis presents a unified SRAM design framework across four linked technical levels: sense amplifier, SRAM bit-cell, SRAM-IMC macro, and reconfigurable SRAM-IMC array. The sense amplifier is studied first because reliable and fast sensing is essential for both conventional SRAM readout and SRAM-IMC output generation. The SRAM bit-cell is then investigated because storage stability, write ability, half-select immunity, and low-voltage robustness originate at the cell level. The scope of the work is further extended to SRAM-IMC macro-level Boolean logic, where stored operands are used directly in the memory structure to reduce data movement. Finally, a reconfigurable SRAM-IMC array is developed to evaluate whether the proposed memory-compute approach remains useful when operated in both memory and compute modes under array scaling. Thus, the thesis treats SRAM throughput enhancement as a co-design problem involving sensing margin, bit-cell robustness, local Boolean computation, and array-level scalability. First, two modified decoupled sense amplifier structures, namely the modified decoupled sense amplifier (MDSA) and the modified decoupled sense amplifier with NMOS foot-switch (MDSANF), are proposed for low-voltage di!erential SRAM sensing. In both topologies, the regenerative latch is decoupled from the bit-lines during the precharge phase and is enabled only after su”cient input di!erential has developed. This operation reduces direct bit-line disturbance and improves read decision speed. At 𝐿DD = 0.8Vand 𝑀BL = 50 fF, the MDSA achieves read-delay reductions of 28.6%, 41.79%, 37.74%, and 30.94% compared with MCSA, DTSA, MHSA,and LSA, respectively. The MDSANF provides comparable delay reductions of 26.13%, 39.78%, 35.58%, and 28.55% with respect to the same reference topologies, while iv the NMOS foot-switch provides additional leakage and evaluation-window control. Monte Carlo analysis confirms improved variation tolerance under threshold-voltage mismatch, and layout evaluation shows practical column-level area overheads of 0.297 𝑁m2 for MDSA and 0.5192 𝑁m2 for MDSANF. The technology-porting study further shows that moving the MDSA from 22 nm FinFET to 32 nm planar CMOS causes only about a 4.5% increase in mean read delay at 𝐿DD = 1V, while reducing the coe”cient of variation from 6.12% to 4.96% and narrowing the delay range by approximately 25%. These results demonstrate that the proposed decoupled sensing approach provides a faster and more variation-tolerant sensing foundation for SRAM and SRAM-IMCdesigns. Second, SRAM bit-cell structures are investigated for improved stability, write ability, energy e”ciency, and robustness under array access conditions. A half-select-free single-ended 8T SRAMbit-cell, referred to as 8TS, is proposed to improve data retention and prevent unintended flipping in selected, half-selected, and unselected cells. At 𝐿DD = 0.8V, the proposed 8TS cell achieves a static noise margin of approximately 0.232 V, a write margin 𝑂𝑃1 = 0.515 V, and a read power of 0.186 𝑁W, while limiting layout overhead to 4.86% relative to the 7T reference. Monte Carlo and process-corner analyses confirm that the cell maintains stable write margin and delay behavior under threshold-voltage variation, supply fluctuation, and temperature variation. In addition, a di!erential 8T SRAM cell, referred to as 8TD, is analyzed and compared with the single-ended 8TS cell. At 𝐿DD = 0.6V, the 8TD cell gives a mean SNM of approximately 0.1932 V with a standard deviation of 0.0056 V, whereas the 8TS cell gives a lower mean SNM of approximately 0.1525 V with a higher standard deviation of 0.0152 V. This confirms that the di!erential cell provides stronger low-voltage stability and tighter mismatch spread. The results indicate that 8TS is suitable for half-select-free and energy-aware storage, while 8TD is suitable for robust di!erential sensing and low-voltage SRAM-IMC operation. The scope of the work is further extended to the design and analysis of an SRAM-IMC macro for bitwise logic implementation. The proposed 8TD SRAM-IMC macro connects two 8TD SRAM cells in a column-wise arrangement to store operands 𝑄 and 𝑅, and uses the shared bit-line behavior together with modified sensing to implement NAND/NOR and XOR/XNOR logic. In this approach, Boolean computation is performed inside or near the SRAM structure without transferring the operands to an external logic unit. Functional simulations verify correct operation for all input combinations, 𝑄𝑅 = 00,01,10, and 11. For NAND/NOR operation, 6000 Monte Carlo simulations are performed at 𝐿DD = 0.8V, 𝑆 = 300.15 K, and ω𝐿TH = 50 mV. The output levels remain clearly separated for all operand combinations, the worst-case mean delay remains close to 0.4 ns, and the coe”cient of variation remains below approximately 2.5%. For XOR/XNOR operation, 2000 Monte Carlo simulations give mean delays of 0.55425 ns and 0.55450 ns, respectively, with standard deviations close to 0.0165 ns. The very small di!erence between the complementary XOR/XNOR mean delays confirms that the logic paths are well balanced under mismatch. Comparative SRAM-IMC cell analysis further shows that the 8TE structure is more suitable for speed-oriented operation, achieving 381.097 ps latency and 2.624 GOPS throughput at 𝐿DD = 0.8V. The 8TC cell provides the lowest energy per bit, but v with higher latency. The proposed 8TD cell provides energy reduction of about 60%–70% at 𝐿DD = 0.5–0.7V, about 30%–40% near nominal supply, and about 15%–25% at higher supply voltages with respect to the 6T, 8TB, and 8TE high-speed baselines. These results clarify the speed–energy trade-o! among the evaluated SRAM-IMC cells. Finally, a dual-mode reconfigurable SRAM-IMC array is proposed for both memory and compute operations. The architecture integrates the proposed 8TD SRAM cell, modified sensing strategy, and Boolean compute path into a common array framework. In memory mode, the array performs conventional SRAM readout, where the selected bit-cell develops a di!erential BL/BLB response that is amplified by the sense amplifier. In compute mode, the same bit-line and sensing infrastructure is reused to generate NAND, NOR, XOR, and XNOR logic outputs. The proposed array is evaluated from 2→2 to 32→32 across𝐿DD = 0.6–1.2V. In memory mode, the static noise margin remains nearly invariant with array size, with relative SNM variation within approximately ±0.6 mV, confirming that storage stability is preserved under the evaluated array scaling. In compute mode, NAND-evaluation latency decreases from approximately 493–517 ps at 0.6Vto approximately 380–388 ps at 1.2V. Over the same supply range, throughput increases from approximately 2.1–2.3 GOPS to approximately 2.75–2.85 GOPS. These results show that speed and throughput scale favorably with supply voltage and remain relatively stable across the evaluated array sizes. However, the average compute energy per bit increases strongly with both array size and supply voltage. The 32 → 32 array is roughly 102 times more energy-consuming than the 2 → 2 array, and its energy increases by about 25→–30→ from 0.6Vto 1.2V. This establishes that switched bit-line capacitance, interconnect loading, precharge activity, and peripheral capacitance are the dominant array-level scaling costs. Overall, this thesis establishes SRAM throughput enhancement as a co-design problem involving bit-cell stability, bit-line development, sense-amplifier timing, local Boolean logic, and array-level energy scaling. The MDSA and MDSANF provide the sensing foundation for fast and variation-tolerant di!erential SRAM readout. The 8TS cell is preferable for energy-aware and half-select-resilient storage. The 8TD cell is suitable for robust di!erential SRAM-IMC operation. The 8TEstructure is suitable for speed- and throughput-oriented SRAM-IMC. The proposed 8TD cell provides a stronger energy-oriented SRAM-IMC option. The reconfigurable SRAM-IMC array demonstrates that the same memory infrastructure can support both conventional read operation and local Boolean computation. At the same time, the array-level results identify compute energy growth under scaling as the main direction for future optimization. Thus, the present research work provides a circuit-to-array SRAM-IMC framework for low-voltage, energy-aware, and throughput-oriented memory-centric computing.