STUDY AND DESIGN OF HIGH PERFORMANCE SAR-ADC

Abstract

The rapid advancement of modern electronic systems has significantly increased the demand for efficient interfaces bridging continuously varying physical signals and digital processing architectures. Modern applications such as Internet of Things (IoT) infrastructures, wireless sensing systems, wearable medical devices, biomedical instrumentation, industrial control platforms, environmental monitoring networks, autonomous systems, and portable electronics rely on continuous acquisition of analog data and its subsequent processing in digital environments. As a result, Analog-to-Digital Converters (ADCs) have become one of the fundamental components of modern mixed-signal integrated systems. The performance of an ADC directly affects the overall accuracy, speed, reliability and energy efficiency of the entire electronic system. Consequently, the optimization of ADC architectures for achieving superior performance and lower energy consumption has become a major focus in integrated circuit design. Among various ADC architectures, Successive Approximation Register (SAR) ADC has emerged as the most attractive solutions for medium-to-high resolution applications owing to its simplified architecture, digital-friendly implementation and excellent energy efficiency. Unlike pipeline ADCs that require power-hungry operational amplifiers or flash ADCs that require a large number of comparators, SAR ADC architectures perform conversion by progressively refining the digital estimate of the input signal using a comparator, Capacitive Digital to Analog Converter (CDAC) and successive approximation control. These advantages make SAR ADCs highly suitable for low-power applications operating under strict energy constraints. However, despite their inherent efficiency, conventional SAR ADCs still face several performance limitations. Comparator delay, DAC switching energy, capacitor area, settling time, power, energy efficiency and SAR control overhead significantly influence the achievable speed, resolution and power consumption of the converter. Furthermore, continued CMOS technology scaling introduces additional challenges such as reduced voltage headroom, increased leakage currents, device mismatch and degraded analog circuit performance. iv Motivated by these challenges, this thesis presents a comprehensive investigation of advanced circuit and architectural techniques aimed at improving the performance of SAR ADCs while maintaining low power consumption and high conversion efficiency. The work begins with a detailed study of ADC fundamentals, performance parameters and existing literature survey. Important SAR ADC performance metrics including resolution, sampling rate, conversion time, Signal-to-Noise Ratio (SNR), Signal-to-Noise-and-Distortion Ratio (SNDR), Spurious-Free Dynamic Range (SFDR), Effective Number of Bits (ENoB), Differential Nonlinearity (DNL), Integral Nonlinearity (INL) and Figure of Merit (FoM) are examined to establish the theoretical framework for evaluating converter performance. A comprehensive study is then conducted covering advanced mixed signal circuit techniques including conventional comparator architectures, DAC switching algorithms, capacitor array optimization techniques, SAR logic implementations and hybrid ADC architectures. Through this survey, several research gaps are identified, particularly in comparator design, switching energy reduction, control logic optimization and high-speed hybrid conversion methodologies. To address the limitations of conventional comparators, the thesis proposes and investigates multiple comparator architectures employing different circuit enhancement techniques. Initially, self-cascode based comparator architectures are developed to improve voltage gain and regenerative behavior while maintaining low static power dissipation. The self-cascode structure effectively increases output resistance and enhances amplification without requiring additional power consuming stages. Subsequently, shared-charge reset mechanisms and auxiliary inverter techniques are introduced to reduce comparison delay and accelerate the regeneration process. These methods improve the charging and discharging characteristics of internal nodes, thereby enhancing comparator speed and reducing energy consumption. Furthermore, Dynamic Threshold MOS (DTMOS)-based comparator architectures are proposed to enable reliable low-voltage operation. By dynamically connecting the gate and body terminals of transistors, the threshold voltage is adaptively controlled during circuit operation, resulting in improved current drivability, faster decision making, and enhanced sensitivity under reduced supply voltages. Detailed circuit-level simulations are performed to evaluate propagation delay, power consumption and energy efficiency. Comparative analysis among all proposed comparator architectures identifies the most suitable design for integration into low-power SAR ADC systems. v Building upon the optimized comparator structure, a low-power 10-bit SAR ADC architecture is designed and implemented. The proposed ADC incorporates a bootstrap switch to improve sampling linearity and minimize signal-dependent resistance variations. The bootstrap circuit ensures a nearly constant gate-source voltage across the sampling transistor, thereby reducing distortion and enhancing input signal fidelity. In addition, a modified split-capacitor DAC architecture is employed to reduce total capacitance and silicon area. The capacitor array is segmented into coarse and fine sections, significantly lowering the overall capacitor requirement while preserving conversion accuracy. To further improve energy efficiency, a Vcm-based switching methodology is adopted. Unlike conventional switching techniques that repeatedly connect capacitors between reference voltages, the proposed approach utilizes the common-mode voltage as an intermediate reference level, thereby reducing charge redistribution energy. An additional energy optimized switching strategy is developed to minimize unnecessary capacitor transitions during successive approximation, resulting in substantial reductions in DAC switching energy and dynamic power consumption. To overcome the speed limitations associated with conventional SAR conversion, a novel Hybrid Flash-SAR ADC architecture is proposed. The hybrid architecture integrates the advantages of flash and SAR conversion techniques to simultaneously achieve high conversion speed with reduced power consumption. In the proposed design, a 4-bit flash ADC front-end performs coarse quantization of the input signal and generates the four most significant bits (MSBs). The flash stage utilizes multiple comparators operating in parallel, enabling instantaneous determination of the coarse digital code. Rest six least significant bits (LSBs) are then resolved by a SAR ADC back-end employing a segmented split-capacitor DAC and asynchronous control logic. By pre-determining the MSBs through flash conversion, thereby decreasing the total number of successive approximation cycles required for conversion, resulting in lower conversion latency and higher sampling speed. A dedicated output encoding and bit-concatenation architecture is also developed for the hybrid converter. The thermometer-coded outputs generated by the flash ADC are converted into binary format using a thermometer-to-binary encoder. These encoded MSBs are synchronized using D flip-flops and combined with the LSBs generated by the SAR ADC through an output assembler block. The resulting architecture produces a complete 10-bit vi digital output while ensuring proper timing synchronization between the flash and SAR conversion stages. Furthermore, asynchronous SAR logic is employed to eliminate unnecessary clock cycles and reduce conversion delay, enabling faster operation compared with conventional synchronous SAR controllers. Extensive simulation studies are carried out using Cadence Virtuoso in a CMOS technology environment to validate the proposed architectures. The performance of individual circuit blocks, including the comparator, DAC, SAR logic, encoder and hybrid conversion system, is thoroughly analyzed. Static performance evaluation includes DNL and INL measurements to assess converter linearity. Dynamic performance is evaluated using FFT based analysis from which SNDR, SFDR, Total Harmonic Distortion (THD) and ENoB are extracted. Power consumption, switching energy, conversion delay and energy efficiency are also investigated in detail. Comparative analysis against conventional switching techniques such as monotonic switching, Vcm-based switching and split capacitor switching demonstrates significant reductions in switching energy achieved by the proposed methodology. Similarly, the proposed hybrid architecture exhibits improved conversion speed while maintaining low power operation compared with traditional SAR ADC designs. The research contributions presented in this thesis provide improvements at both circuit and system levels. At the circuit level, novel comparator architectures based on self-cascode, shared-charge, auxiliary inverter and DTMOS techniques enhance speed, sensitivity and energy efficiency. At the architectural level, the proposed split-capacitor DAC, energy efficient switching methodology, asynchronous SAR logic and Hybrid Flash-SAR conversion approach collectively reduce power consumption, switching energy and conversion latency. These contributions provide a systematic foundation for developing next-generation ADC architectures with improved energy efficiency and enhanced performance. The outcomes of this research have significant practical relevance for modern electronic systems operating under stringent energy constraints. The proposed ADC architectures are particularly suitable for IoT sensor nodes, wearable health-monitoring devices, biomedical instrumentation, wireless communication transceivers, environmental monitoring platforms, smart industrial systems and battery-powered portable electronics. Furthermore, the developed methodologies provide a foundation for future investigations into ultra-low vii voltage operation, advanced CMOS technology scaling, adaptive calibration techniques, artificial intelligence-assisted data conversion systems and high-speed mixed-signal integrated circuits. Consequently, the work presented in this thesis contributes toward the development of energy-efficient and sustainable electronic systems capable of supporting the growing demands of future digital technologies.