Please use this identifier to cite or link to this item: http://dspace.dtu.ac.in:8080/jspui/handle/repository/23367
Title: LOCK-TIME REDUCTION IN SUB-SAMPLING PHASE-LOCKED LOOPS USING ADAPTIVE VCDL GAIN
Authors: ARYA, GURVINDER
Majumdar, Sudipta (SUPERVISOR)
Keywords: SUB-SAMPLING PLL
VOLTAGE-CONTROLLED DELAY LINE
ADAPTIVE GAIN SCHEDULING
DISCRETE-TIME STABILITY
LYAPUNOV STABILITY
CADENCE VIRTUOSO
SPECTRE SIMULATION
LOCK TIME
RING VCO
SSPLL
VCDL
Issue Date: May-2026
Series/Report no.: TD-9177;
Abstract: Sub-sampled phase-locked loops employing ring oscillators provide several bene fits for modern integrated circuits, including a small size, broad range of tunability, and easy transfer between nodes. They do not suffer from the added noise resulting from a feedback divider either. Unfortunately, there is an important drawback to consider. At high output frequencies, the loop gain can be too high and cause loss of stability on the intrinsic feedback path. Though the traditional remedy, adding a voltage-controlled delay line, will guarantee stability, it will cause the loop to take a long time to settle, oscillating with each iteration of the phase error until it finally settles down. This project report takes a different view of the delay line. Rather than treating its gain as a fixed design constant, it is treated as a quantity that can be varied on the fly according to how large the phase error currently is. A smooth scheduling law keeps the gain high while the loop is still acquiring, which suppresses the oscillatory behaviour and lets the error fall away rapidly, and then relaxes the gain gently back to its nominal value once the loop has nearly settled. A central concern throughout is that this changing gain must never compromise stability, and a Lyapunov-based argument is developed to show that the loop remains stable for every admissible phase error as the schedule moves through its range. The proposed loop is studied through behavioural circuit simulation in Cadence Virtuoso and Spectre, using models of the sub-sampling detector, the delay line, the adaptive scheduler, the ring oscillator, and an automated lock-time detector. The re sults show that the adaptive scheme locks substantially faster than the conventional v fixed-gain design, with the advantage becoming more pronounced as the size of the disturbance grows, and that this speed-up is obtained without any penalty to the settled noise performance and without adding extra detectors, filters, or injection paths. In short, fast and clean acquisition is recovered for a ring-oscillator sub-sampling loop simply by varying one parameter that the loop already contains.
URI: http://dspace.dtu.ac.in:8080/jspui/handle/repository/23367
Appears in Collections:M.E./M.Tech. Electronics & Communication Engineering

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