COMPARATIVE ANALYSIS OF VOLTAGE MODE SENSE AMPLIFIERS WITH MODIFIED DECAP-ASSISTED PRECHARGE TECHNIQUE

Abstract

Static Random Access Memory (SRAM) is one of the most important memory components used in modern digital systems such as microprocessors, cache memory, mobile devices and embedded applications because of its high speed, low latency and reliable performance. During the read operation of SRAM a very small voltage difference is generated between the bit-lines. This small signal cannot be directly detected by digital circuits. therefore, a sense amplifier is required to sense and amplify the signal into a full logic level. The performance of the sense amplifier plays a significant role in determining the speed, power consumption, stability and reliability of the SRAM system. As CMOS technology continues to scale down, designing an efficient sense amplifier becomes more challenging due to reduced sensing margin, increased leakage current, process variations and higher bit-line capacitance. Several voltage-mode sense amplifiers such as Cross-Coupled Voltage Sense Amplifier (CCVSA), Latch-Type Sense Amplifier (LTSA), Transmission-Gate Sense Amplifier (TGSA), Parallel Latch-Type Sense Amplifier (PLTSA) and Decoupled Inverter Pair Sense Amplifier (DIPSA) have been proposed in previous research works. Each architecture provides different advantages and limitations in terms of delay, power consumption and stability. Some designs offer high sensing speed but consume more power while others provide low power consumption at the cost of increased delay. Therefore, there is a need for a sense amplifier that can achieve a better balance between speed, power efficiency and stable operation under different operating conditions. In this work, a Modified Decap-Assisted Sense Amplifier (MDASA) is proposed to improve sensing performance in SRAM applications. The proposed architecture uses decoupling capacitors and parallel transistor paths to provide additional charge support to the bit-lines and improve drive strength during sensing operation. Initially the decoupling capacitors are charged using control signals and during sensing the stored charge is transferred to the bit-lines to provide an initial voltage boost. A cross-coupled positive feedback structure is used to amplify the small voltage difference rapidly and generate a stable digital output. The use of parallel transistor paths further enhances sensing speed and reduces sensitivity to bit-line capacitance variations. The proposed MDASA and other conventional sense amplifiers are simulated using LTspice in 45 nm CMOS technology under uniform operating conditions. The supply voltage is varied from 0.7 V to 1.2 V and bit-line capacitance is varied from 50 fF to 250 fF. Performance analysis is carried out based on important parameters such as delay, power consumption, leakage current and Power-Delay Product (PDP).The proposed MDASA achieves simulation results that show the lowest delay among all compared sense amplifiers indicating the fastest sensing performance. The design also shows an improved Power-Delay Product which represents better energy efficiency. Although CCVSA provides the lowest power consumption and leakage current, MDASA achieves a better overall trade-off between speed, power and stability. The proposed architecture also demonstrates stable operation under varying supply voltages and bit-line capacitance conditions. Therefore, the proposed MDASA is highly suitable for high-speed and energy-efficient SRAM applications in modern VLSI systems.