COMPARATIVE STUDY OF FPGA-BASED PERFORMANCE EVALUATION OF LMS, NLMS,AND RLS ADAPTIVE FILTERS FOR NOISE CANCELLATION

Abstract

This thesis presents a systematic comparative study and FPGA hardware imple mentation of six adaptive filter algorithms — LMS, Sign-LMS, NLMS, VSS-LMS, VSS-Sign-LMS, and RLS — for real-time speech noise cancellation targeting 50 Hz sinusoidal power-line interference at a sampling frequency of 8 kHz. The work is organized into three sequential phases: MATLAB-based algorithm simulation and performance evaluation, 16-bit Q15 fixed-point Verilog RTL design and FPGA syn thesis on the Xilinx Kintex-7 xc7k70tfbv676-1 device using Vivado 2023.2, and a comprehensive multi-metric comparative analysis of all six algorithms under identical hardware constraints. A systematic filter order analysis established that N = 1 is the optimal filter config uration for all six algorithms in single-tone noise cancellation, as higher filter orders introduce weight-misadjustment noise that degrades output SNR monotonically. MAT LAB simulation with 16,000 samples under identical signal conditions — a composite speech signal (300 Hz and 700 Hz) corrupted by 50 Hz power-line noise at an input SNR of −0.06 dB —confirmed VSS-LMS as the best-performing algorithm, achieving an output SNR of 27.02 dB, convergence time of 1.25 ms, and a final adaptive weight of 0.8998, the closest approximation to the true noise transfer function coefficient of 0.9 among all evaluated algorithms. The VSS-LMS variable step-size mechanism, governed by the update rule µ(n+ 1) =clipα·µ(n)+γ·e2(n), µmin, µmax with α =0.99 and γ =0.0001, resolves the fundamental convergence-speed versus steady-state error trade-off inherent in all fixed step-size algorithms. By driving the step size toward µmax during initial convergence and toward µmin at steady state, VSS-LMS achieves both fast weight adaptation and low steady-state misadjustment, enabling it to surpass even the Recursive Least Squares algorithm (RLS: 25.26 dB) in steady-state noise suppression. Post-implementation results from Vivado 2023.2 confirm that VSS-LMS utilizes only 132 Slice LUTs (0.32% of available resources), 142 flip-flops, 5 DSP48E1 slices, and 0.137 W total power, with a Worst Negative Slack (WNS) of +4.686 ns and an estimated maximum operating frequency (Fmax) of approximately 188 MHz. Coun terintuitively, VSS-LMS consumes fewer LUTs than the standard LMS algorithm (197 LUTs) despite requiring three multiplications per update versus LMS’s two. This arises from Vivado DSP48E1 cascade inference: the linear µ ·e·x multiplication chain is absorbed end-to-end into five DSP48E1 primitives, eliminating LUT-based multiplier logic entirely. The NLMS and RLS algorithms fail to meet the 100 MHz timing con straint with WNS ≈ −45 ns and 16 failing endpoints each, attributable to a sequential division circuit — the normalization denominator in NLMS and the Kalman gain in RLS — creating a combinational path of approximately 55 ns, more than five times the 10 ns clock period. ABSTRACT vi Application-specific selection guidelines are established from the experimental results. VSS-LMS is recommended as the primary choice for real-time FPGA adap tive noise cancellation systems requiring maximum noise suppression. Sign-LMS is identified as the preferred algorithm for ultra-low-power IoT and battery-operated de vices, offering the lowest power consumption (0.134 W) with zero DSP48E1 utilization. VSS-Sign-LMS is recommended for DSP-resource-constrained multi-channel systems, achieving a 60% reduction in DSP48 usage relative to VSS-LMS with an estimated Fmax of approximately 200 MHz. Standard LMS remains a reliable general-purpose baseline with predictable convergence behaviour. NLMS and RLS require architectural redesign — involving pipelined division or systolic array decomposition respectively — before practical 100 MHz FPGA deployment becomes feasible. The principal contributions of this thesis are: (i) the first unified FPGA comparative study of six adaptive filter algorithms under identical 16-bit fixed-point precision, 100 MHz timing constraint, and speech noise cancellation conditions on the Kintex 7 platform; (ii) demonstration and explanation of the VSS-LMS resource-efficiency paradox via DSP48E1 cascade inference; (iii) detailed timing failure analysis of NLMS and RLS at 100 MHz, with quantitative evidence identifying the specific circuit element responsible; and (iv) complete Verilog RTL implementation and testbench verification of all six algorithms with all results derived from actual Vivado tool runs rather than analytical estimates.