DESIGN AND ANALYSIS OF POSITIVE FEEDBACK SOURCE COUPLED LOGIC FOR PERFORMANCE ENHANCEMENT

Abstract

With the rising demand for portable and low-power electronic systems such as consumer gadgets, biomedical implants, and sensor nodes, the design of mixed-signal systems that place both analog and digital circuits on a single chip have become increasingly important. Such integration benefits from fewer interfaces, lower power consumption and higher speed. In mixed-signal systems, the switching noise generated in digital blocks can adversely affect the performance of on-chip analog circuitry. In CMOS logic, this noise arises from current spikes and transient voltage fluctuations during switching. To mitigate these effects, several techniques at the various levels of abstractions have been developed. Among them, low switching-noise logic families have gained attention, as they maintain nearly constant supply current during transitions and operate with smaller voltage swings. Some notable logic styles are current steering logic (CSL) style, current balance logic (CBL) style, folded source coupled logic (FSCL) style and the source coupled logic (SCL) style. Positive feedback is introduced in SCL wherein the reference voltage source is omitted for improving speed. The resulting logic family is called positive feedback source coupled logic (PFSCL) which has emerged as a promising option due to its inherently low noise switching characteristics. The PFSCL gates are primarily based on NOR/OR gates and hence infer cascading of gates of complex logic function realization. The existing PFSCL fundamental cell-based gates enable single stage realization of complex logic functions by accommodating two or more minterms, however, they occupy larger area. This work investigates PFSCL circuits and presents design enhancements aimed at improved overall efficiency. Here, the memristors are integrated into the PFSCL realization to improve integration density and performance. Two designs are proposed, the first design incorporates memristors into the PFSCL inverter whereas the second integrates memristors into the PFSCL NOR/OR gate. The proposed designs have reduced gate count in comparison to PFSCL NOR/ OR gates, and reduced footprint than fundamental cell-based realization, thus leading to lower propagation delay and reduced power consumption. Owing to positive feedback, low voltage swing and presence of constant current source, the PFSCL style is known for high-speed operation. There is static power consumption in the circuit which limits its usage in battery-powered applications. The dynamic PFSCL (D-PFSCL) has been introduced to reduce power consumption wherein dynamic current source is employed in place of constant current source. The earlier work on D-PFSCL gates focused primarily on improving dynamic current source and enhancing logic implementation using fundamental cells and transmission gates. The logic implementation occupies larger area, therefore memristors are incorporated in D-PFSCL design which not only reduce cascading for complex function realizations, but also improve footprint. The registers are vital components used widely for data storage, data manipulation, and temporary data storage in high-performance computing used in SoC realizations. viii The CMOS registers suffer from high switching noise and fail to provide an analog friendly environment in mixed-signal applications. Also, the significant power consumption at high operating frequency needs attention. To bridge this gap, PFSCL registers are designed. The available switch and sleep based tristate PFSCL buffers/inverters are used to realize to static and dynamic PFSCL registers. These registers are based master slave approach wherein clock and its complement are used for proper operation. The issue of clock-skew is analyzed and a solution is also suggested to overcome this. The operation of PFSCL gates developed using metal oxide semiconductor field-effect transistor (MOSFET) in deep submicron nodes deteriorate due to short-channel effects, leakage, and mobility degradation. The carbon nanotube FETs (CNTFETs) have emerged as a viable alternative owing to their near-ballistic transport, high mobility, and low leakage. The nonavailability of PFSCL circuit realizations in CNTFET is addressed next in this work. It is found that there is significant improvement in propagation delay. All the proposed designs are functionally validated through extensive SPICE simulations using PTM 90 nm technology parameters. The proposals are also laid out using Microwind to asses area efficiency. The performance of the proposals is compared with existing counterparts in terms of propagation delay, power consumption, power delay product and area. Additionally, Stanford University 32 nm CNTFET model is used to validate the performance of CNTFET based gates.