DESIGN AND PERFORMANCE OPTIMIZATION OF NANO SCALE VEDIC MULTIPLIER ARCHITECTURE

Abstract

The persistent trend towards device miniaturization of electronic devices has made apparent the structural and operational limitations of the conventional CMOS tech nology such as increased leakage currents, excessive power dissipation, and challenges in further scaling. These issues have become critical bottlenecks to the sustained evolution of high-performance, energy-efficient computing systems. Thus, it is imper ative to explore alternative paradigms that can sustain the trajectory of Moore’s law while overcoming the inherent drawbacks of conventional transistor-based designs. Quantum-Dot Cellular Automata (QCA) has emerged as a compelling post-CMOS technology, offering computation through the manipulation of electron positions rather than current flow. This unique mechanism enables ultra-low power operation, high device density, and fast switching speeds, positioning QCA as a promising candidate for next-generation nanoelectronic circuits. This thesis aligns with this paradigm shift by addressing the critical challenge of efficient multiplier design through the integration of Vedic mathematics with QCA and reversible logic principles. The primary objective of this research is to develop scalable, low-power Vedic multiplier architectures that are both computationally efficient and suitable for nano electronic implementation. To achieve this, the research begins with the development and evaluation of novel 4-bit and 8-bit CMOS-based Vedic multiplier architectures, establishing a performance baseline and highlighting the constraints posed by CMOS technology in terms of energy and delay. Building on this foundation, the research transitions into the QCA domain, where energy efficient adder layouts such as half adder and full adder are designed with only viii 23 and 40 QCA cells respectively which serve as building blocks for advanced adders such as Ripple Carry Adders (RCAs) and Carry Save Adders (CSAs). These de signs incorporate coplanar and multilayer crossover strategies to address interconnect complexity while minimizing area and latency. It can be noted that the suggested RCA and CSA designs demonstrate notable improvements in designs metrics and outperform the latest reported design in terms of quantum cost by 38% and 68.9% respectively. Further, a comprehensive evaluation of energy efficiency, and thermal behavior under varying cell sizes is conducted using QCADesigner-E and QCAPro tools. The obtained results validate the energy-efficient characteristics of the pro posed circuits, with the RCA and CSA exhibiting very low energy dissipation values of 5.27×e−003 eV and 9.68×e−002 eV, respectively. Leveraging these optimized adder designs, the research further proposes novel Vedic multiplier architectures with significant improvements in computational efficiency and an impressive 81.35% reduc tion in cost with a reduced number of crossovers as compared to the recent single-layer design underscoring it’s suitability for nanoelectronic applications. In the final phase, the study introduces reversible logic into the QCA framework to further enhance energy efficiency and reduce computational overhead. Accordingly, a reversible Vedic multiplier (RVM) is developed using optimized co-planar imple mentations of the Peres and BVPPG gates, requiring only 221 QCA cells with a very small latency of 1.5 clock cycles and total energy dissipation of 5.58×e−002eV while also reducing the number of constant inputs and garbage outputs. Collectively, these contributions reflect a systematic and innovative approach to arithmetic circuit design, combining ancient computational methods with emerging nanoelectronic technologies. The proposed architectures exhibit strong potential for use in high-performance, low-power applications such as signal processing, cryptog raphy, biomedical electronics, and next-generation arithmetic processors.