ML-ASSISTED DESIGN AND OPTIMIZATION OF ANALOG INTEGRATED CIRCUITS

Abstract

This thesis proposes a machine-learning assisted framework for process-variation aware transistor sizing of CMOS current mirrors, based on foundry-accurate Spectre simulations in a 45-nm technology node. The paper addresses a long-standing problem in analog integrated circuit design: the difficulty of systematically optimizing nonlinear circuit blocks, when device parameters, process variations, and design constraints are competing. Current mirrors are one of the most basic building blocks in analog and mixed-signal systems. They are extensively used in bias generation, current replication, and signal conditioning and their performance directly affects current accuracy, power consumption, compliance voltage and robustness. The design of current mirrors has been based on manual iteration and SPICE simulation. It is a time consuming process and highly dependent on the expertise of the designer. At smaller technology nodes short channel effects, mobility degradation, oxide thickness variation and mismatch become more important and sizing becomes harder. To tackle this issue, the present work proposes a data-driven approach based on 50,000 simulation points generated through foundry-accurate Spectre simulations with BSIM4.5 device models. The data set includes various transistor sizing parameters, operating conditions, and global process variation parameters such as mobility variation and oxide thickness variation. For prediction of current errors, power consumption, compliance voltage and process-variation sensitivity, supervised ensemble learning models such as Random Forest and Gradient Boosting regressors are used. The proposed framework shows good prediction accuracy and reveals important dependencies between transistor dimensions and circuit behavior. In particular, the results indicate that features related to width-to-length ratios and output resistance have a significant impact on current accuracy and sensitivity to variations. The machine learning-guided optimization step finds transistor widths that satisfy design constraints on error, power, and compliance voltage while greatly reducing the iteration time compared to manual SPICE-based exploration. The thesis presents a reproducible and scalable methodology for analog design automation. It bridges physical circuit simulation and data-driven optimization and demonstrates that machine learning can be a promising aid for robust transistor sizing in advanced CMOS technologies. The results are relevant for research and industrial analog design flows, especially when speed, robustness and accuracy have to be balanced simultaneously..