LOW POWER DYNAMIC TSPCD FLIP-FLOP FOR HIGH PERFORMANCE APPLICATIONS BASED ON CNTFET

Abstract

In today’s Very Large Scale Integration (VLSI) systems, low power and high speed sequential circuits havebecomemoreandmoreimportantduetothedemandforportable and high performance electronic systems. The digital circuits have different sequential elements which are important building blocks in digital circuits, which is the D flip flops used in digital circuits are widely used in digital circuits which include registers, counters, memory elements and digital signal processing systems. But, there are significant problems with the conventional CMOS technology at nanoscale dimension like the leakage current, power dissipation and short channel effect. In this thesis, a comparative performance analysis of the two types of True Single Phase Clocked D Flip Flops(TSPCDFF):CMOSandCNTFEThasbeenperformedat22nmtechnology. Four different TSPC D flip-flop architectures, conventional TSPC, modified TSPC, preset enabled modified TSPC and redundant precharge-free TSPC D flip-flop architectures, have been investigated. Evaluation of the performance is done on the basis of important parameters like Average power consumption, leakage current, propagation delay, Power Delay Product. Theoutcomes of the simulation confirm that theCNTFETbased architectures offerhigh performance compared to CMOS based architectures. The redundant precharge-free CNTFET based TSPC D flip-flop was found to have the minimum PDP value among all the analysed architectures, which means that it has the lowest energy consumption and is best suited for the future low power high speed VLSI applications.