DESIGN OF MEMELEMENTS AND ITS APPLICATION IN MIXED SIGNAL PROCESSING CIRCUITS

Abstract

Memristor technology is gaining popularity for its potential uses in nanoelectronic memory, neuromorphic computer architectures, digital and analog modulation systems, and oscillator circuits. Memristor research has becoming increasingly popular. However, there is currently no single device on the market that can display true memristive behavior over a specific frequency range. Researchers rely on emulator circuits to study the features and possible uses of physical memristor prototypes, which are presently restricted. Memristor emulator circuits simulate the behavior and attributes of memristors. Memristors are a newly recognized passive element with potential uses in digital, analog, and mixed signal domains. Emulator circuits are crucial for understanding the underlying concepts and potential uses of memristors, especially in the absence of a physical memristor. They can be made in the lab using inexpensive off-the-shelf components. Prof. L Chua profound a new circuit component in 1971 which behaves differently in comparison to three known passive components (resistor, capacitor, and inductor). After three decades, in 2008, D. B. Strukov and his team presented the first fabricated memristor and after a long gap (four decades), the concept of memelements extended to memcapacitor and meminductor. The researchers are keenly interested in exploring the characterization and application in different fields of memelelements because of their non-linear and non volatile properties. Further, the lack of fabrication-level implementation, researchers is trying to develop their circuit emulators and rely on this practical approach. Mostly existing circuit emulators are thoroughly analyzed, simulated, and summarized in detail with the different approaches. Hence, This thesis presents a comprehensive study and novel design methodologies for compact, low-power emulator circuits of emerging memory-based elements—namely memristors, memcapacitors, and meminductors—using CMOS compatible technologies. Multiple emulator topologies have been proposed, each targeting specific performance metrics such as high-frequency operation, low power consumption, and hardware simplification. These circuits are realized through innovative configurations of MOSFETs, MOS capacitors (MOSCAPs), operational transconductance amplifiers (OTAs), differential mode floating gate (DMFG), gyrator circuit, and dynamic threshold techniques. A compact memristor emulator design is presented, demonstrating different circuit approaches. The first design is a FMRE- floating memristor emulator and GMRE- grounded memristor emulator that uses a single MOSFET with a RC filter which is first viii order, achieving operating frequencies up to 80 MHz within a compact 1.586 μm² layout. The second design is a MOSCAP-based grounded passive memristor emulator, implemented with only MOSFETs (three numbers) and MOSCAP (one number), requiring no external biasing and emphasizing simplicity and power efficiency, with reliable operation up to 30 MHz. The third approach introduces a floating, fully passive memristor emulator that consists of MOSFETs (six numbers) and capacitor (one number), employing the DTMOS-dynamic threshold MOSFET technique. These circuits are analyzed through their hysteresis loops and current–voltage characteristics, confirming the expected memristor figures of merit. Furthermore, the proposed emulators are demonstrated in mixed-signal processing applications, including filters, Schmitt triggers, Colpitts oscillators, Chua’s oscillators, and XOR logic circuits. For memcapacitor emulation, a design using a single multi-output OTA is proposed and validated through both 45nm CMOS simulation and hardware testing using the LM13700 IC. This circuit supports operations up to 4 MHz, consuming 272.5 µW, and proves suitable for integration, differentiation, and neuromorphic learning tasks. Robustness is confirmed via Monte Carlo and PVT variation analyses. Meminductor emulator circuits have also been investigated using different design strategies. In one grounded topology, six MOSFETs and two capacitors are employed to generate pinched hysteresis loops (PHL) at an operating frequency of 100 kHz, with performance validated through comprehensive PVT (process, voltage, and temperature) analysis and non-volatility testing. Another advanced design is based on an active gyrator configuration that utilizes five MOSFETs, including a MOS-based capacitor. This design achieves a high operating frequency of 200 MHz, with static and dynamic power consumptions of 2.52 mW and 3.23 mW, respectively, while occupying an area of 80.5 μm². The practicality of these emulators is further demonstrated by their application in adaptive learning systems and chaotic oscillator circuits. All emulator circuits are designed and simulated using Cadence Virtuoso Spectre tool with GPDK 180nm, 90nm, and 45nm CMOS technologies. Extensive analyses including transient response, hysteresis behavior, non-volatility, tunability, temperature stability, and process corner variation confirm the reliability and scalability of the proposed designs. Comparative studies show significant improvements in circuit simplicity, frequency performance, and power efficiency over existing emulator models. ix These contributions collectively advance the practical realization of memory-based analog components in neuromorphic computing, nonlinear systems, and programmable analog signal processing, thereby supporting the next generation of intelligent hardware platforms. Finally, in this thesis, we summarize the conclusions inferred from our research work and highlight the potential future scope in the field of next generation of intelligent hardware platforms.