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http://dspace.dtu.ac.in:8080/jspui/handle/repository/22976| Title: | COMPARATIVE THD ANALYSIS OF 31-LEVEL AND 63-LEVEL REDUCED SWITCH MULTILEVEL INVERTER WITH PASSIVE FILTER |
| Authors: | LAYBA SINGH, MADHUSUDAN (SUPERVISOR) SREEJETH, MINI ( CO- SUPERVISOR) |
| Keywords: | THD ANALYSIS SWITCH MULTILEVEL INVERTER PASSIVE FILTER |
| Issue Date: | Jun-2026 |
| Series/Report no.: | TD-8877; |
| Abstract: | The Multilevel inverter have gained recognition in last few decades. They are being utilized to convert the DC voltage into AC voltage in the form of steps or levels, with increasing the steps the output voltage start achieving the shape similar to the sine wave which results in reducing the harmonic distortion. However, increasing the levels in output voltage of multilevel inverter leads to increase in the power electronic components and devices which makes the design massive. The Multilevel inverters are widely being used in various applications like renewable energy systems, high power motor drives, HVDC transmission, FACT devices, electric vehicles and many more. A wide range of controlling methods and modulation techniques are being introduced to enhance the efficiency and operation. In our work, we have designed the 31-level and 63-level reduced switch multilevel inverter. Simulation has been carried out using MATLAB Simulink. The load used in the simulation of MLI are taken as R-L load. The Total Harmonic Distortion for each system has also been analyzed and studied from simulation results. The design of the 31-level reduced switch multilevel topology consists of twelve switches and four DC sources and the 63-level topology consists of fourteen switches and five DC sources, aiming to reduce the THD obtained and enhancing its efficiency. In order to further reduce the THD, an LC and LCL filter has been designed, and a comparative THD analysis has been performed by considering the two cases, that is, one without a filter and another with LC and LCL filter. The THD’s observed are falling under IEEE 519 standards, which is below 5%. We have also implemented the design of lower-level reduced switch topologies, which is 5 level and 7-level Reduced Switch MLI and then observed the THD’s. Then, we have designed the LC filter for both topologies and observed the THD’s and compared the results. |
| URI: | http://dspace.dtu.ac.in:8080/jspui/handle/repository/22976 |
| Appears in Collections: | M.E./M.Tech. Electrical Engineering |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| LAYBA M.tech.pdf | 4.43 MB | Adobe PDF | View/Open | |
| LAYBA plag.pdf | 3.93 MB | Adobe PDF | View/Open |
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