DESIGN AND ANALYSIS OF HIGH-SPEED CMOS VOLTAGE LEVEL SHIFTERS FOR SUB-THRESHOLD VOLTAGE REGIME

Abstract

In modern VLSI systems with multiple voltage and low power levels, voltage level shifters (VLSs) are components that allow reliable communication between different voltage domains of the circuit blocks. As the CMOS technology is scaled down and low power consumption in portable electronic devices, biomedical implants, wireless sensor networks, and IoT devices is being demanded continuously, the design of voltage level shifters with low power consumption and high-speed operation has been one of the major research focuses. This comparative study examines a number of recently proposed voltage level shifter architectures, such as conventional cross-coupled level shifters, differential cascode voltage switch (DCVS) structures, current mirror-based level shifters, Wilson current mirror structures, regulated cross-coupled pull-up network (RCC) techniques, and dual current mirror approaches. The primary motivation for the comparative study is the propagation delay, switching speed, power dissipation, voltage conversion, and robustness of the circuit when operating at subthreshold. Conventional cross-coupled and DCVS level shifters have low standby power, but these circuits suffer from the significant problem of contention between the pull-up and pull-down networks at very low input voltage, resulting in larger delay and poor performance. On the contrary, architectures like the current mirror and the Wilson current mirror improve the driving capability and decrease the contention, thus increasing conversion speed and decreasing propagation latency. Propagation delay as low as 0.959 ns and low power dissipation of 106.6 nW for 45 nm technology, making it very energy-efficient for ultra-low voltage applications. The voltage level shifter designed with a regulated cross-coupled pull-up network (RCC) was found to be the best amongst all the techniques considered in terms of both speed and power consumption. The RCC technique has proved to be effective in regulating the pull-up strength, reducing the time of discharging and charging the internal nodes, reducing the static current & greatly increasing the switching speed. The results of the simulation of the RCC-based design resulted in very low power consumption of 123.1nW with a propagation delay of 23.7ns, and it is capable of handling subthreshold input conversion as low as 80 mV. Moreover, optimized device sizing and multi threshold CMOS showed advantages in performance for wider voltage translation ranges and area efficiency for the improved RCC structures.