DESIGN AND ANALYSIS OF A TWO-STAGE BUFFER AMPLIFIER IN 28 nm AND 18 nm CMOS TECHNOLOGIES FOR LOW-VOLTAGE REFERENCE SYSTEMS

Abstract

Voltage reference circuits such as bandgap references, low-dropout regulators, and on-chip bias generators are increasingly required to drive multiple distributed loads inside modern mixed-signal systems-on-chip. To prevent loading and noise coupling, the reference is usually isolated from its loads using an analog buffer amplifier. The buffer is required to provide near-unity voltage gain, high input impedance, low output impedance, sufficient bandwidth to track transient demands, and unconditional stability under closed-loop operation. In aggressively scaled CMOS nodes, the limited intrinsic gain of short-channel devices, the reduced supply headroom, and the increased parasitic capacitance make the design of such a buffer non-trivial. This project report presents the design, analysis, and simulation of a two-stage CMOS buffer amplifier intended for buffering on-chip voltage references of 0.6 V, 1.2 V, and 1.3 V. The buffer is implemented and characterised in both 28 nm and 18 nm CMOS technology nodes. The first stage is realised as a PMOS-input differential amplifier with an NMOS current-mirror load, providing the dominant voltage gain and a low-noise, high-input-impedance front end. The second stage is an NMOS common-source output stage with a PMOS active load, which provides additional gain and improved output drive capability. The amplifier is closed in unity-gain feedback configuration to operate as a buffer, and a series resistor–capacitor (RC) network is connected between the high-impedance node of the first stage and the output node to provide frequency compensation. The RC compensation moves the dominant pole to a lower frequency, splits the non-dominant pole to a higher frequency, and cancels (or moves to the left-half-plane) the right-half-plane zero introduced by the feedforward path through the compensation capacitor, thereby ensuring a phase margin sufficient for stable operation. The proposed buffer targets a nominal unity-gain bandwidth (UGB) of 10 MHz at the typical corner across all three reference voltages and both technology nodes. Transistor-level simulations across the five process corners (TT, SS, FF, SF, FS) demonstrate that, for the 28 nm implementation, the open-loop DC gain spans approximately 85 dB to 110 dB (nominal 92 dB) and the UGB spans approximately v 3 MHz to 40 MHz (nominal 10 MHz). For the 18 nm implementation, the open-loop DC gain spans approximately 82 dB to 103 dB and the UGB spans approximately 5 MHz to 40 MHz. A detailed comparative study between the 28 nm and 18 nm implementations is reported, and the differences observed are explained in terms of intrinsic gain (gm⋅ro), short-channel effects, parasitic capacitance, and the difference in carrier mobility between the two nodes. The project report additionally provides a comprehensive review of frequency compensation techniques used in two-stage operational amplifiers, and discusses the rationale for selecting RC compensation for this work.