Please use this identifier to cite or link to this item: http://dspace.dtu.ac.in:8080/jspui/handle/repository/22925
Title: DESIGN AND ANALYSIS OF PFTFN-BASED GROUNDED CAPACITANCE MULTIPLIER
Authors: KUMAR, PRASHANT
Bhagat, Ram (SUPERVISOR)
Keywords: CAPACITANCE MULTIPLIER
DISCRETE ANALOG CIRCUIT
PSPICE SIMULATION
GROUNDED IMPEDANCE SIMULATOR
CURRENT-MODE SIGNAL PROCESSING
PFTFN
AD844
Issue Date: May-2026
Series/Report no.: TD-8833;
Abstract: Nanofarad-range capacitors are physically large, expensive, and prone to parasitic inductance at high frequencies—posing challenges in discrete-board prototyping, instrumentation, and wearable sensor front-ends. Active capacitance multipliers overcome this limitation by employing a compact physical capacitor and an active element to present a much larger equivalent capacitance to the circuit, with the multiplication factor set by external resistor ratios. Despite several published reali sations using operational transconductance amplifiers and current conveyors, a dis crete implementation based on the Positive Four-Terminal Floating Nullor (PFTFN) has not previously been reported. This dissertation report presents the design and PSpice simulation of a grounded capacitance multiplier using a Positive Four-Terminal Floating Nullor (PFTFN) realised using a discrete two-AD844 circuit. The circuit is derived by rearranging the passive elements of the Kumar–Senani inductance simulator [4], replacing the grounded inductor with a grounded capacitor via a single component substitution. The proposed circuit offers three key advantages: (i) an externally resistor-tunable multiplication factor requiring no IC-level modifications; (ii) a lossless grounded capacitance under a matched-resistor condition; and (iii) a purely current-mode signal path consistent with the PFTFN port constraints. In the two-AD844 discrete realisation, both ICs operate from a ±5V dual supply and their inverting (X) terminals are connected together to approximate the PFTFN current-matching constraint. PSpice parametric sweep simulation confirms that a physical 1nF capacitor produces an equivalent capacitance of approximately 475pF at the baseline resistor setting, tunable down to approximately 205pF by varying a single resistor—a 2.3:1 tuning range. A further sweep confirms that the equivalent capacitance is insensitive to the output-branch resistor when the lossless matching condition holds, consistent with the analytical formula. The circuit maintains flat capacitance from 100Hz to approximately 10kHz, making it well suited to audio and biomedical signal processing applications.
URI: http://dspace.dtu.ac.in:8080/jspui/handle/repository/22925
Appears in Collections:M.E./M.Tech. Electrical Engineering

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