DEEP LEARNING BASED PROPAGATION DELAY PREDICTION AND SENSITIVITY ANALYSIS OF CMOS LOGIC CIRCUITS

Abstract

Propagation delay is one of the most critical performance parameters in CMOS digital circuit design, directly influencing timing closure, clock frequency, and overall system performance. As VLSI technology scales to nanometer nodes, accurate and efficient estimation of propagation delay becomes increasingly important during the design phase. Traditional SPICE-based simulation methods, while highly accurate, are computationally intensive and become impractical for large scale design optimization and exploration. This thesis proposes a deep learning-based approach for predicting propagation delay in fundamental CMOS logic gates — inverter, 2-input NAND, and 2 input NOR — at the 45 nm technology node. A comprehensive dataset of 2500 simulation samples is generated using SPICE-based circuit simulation by varying key circuit parameters including NMOS transistor width (Wn), PMOS transistor width (Wp), channel length (L), supply voltage (VDD: 0.8–1.2 V), load capacitance (CL: 1–20 fF), and temperature (0–100°C). Feature engineering techniques are employed to derive additional physically meaningful parameters such as the transistor width ratio (Wp/Wn) and the RC time constant product. A multilayer perceptron (MLP) based deep learning regression model is developed and trained on the preprocessed dataset.