FGMOS BASED VDTA REALIZATIONS WITH ENHANCED PERFORMANCE

Abstract

This thesis presents a comparative study of floating-gate MOSFET-based voltage differencing transconductance amplifier realizations with the objective of improving low-voltage operation and transconductance performance for analog signal-processing applications. This work consolidates two research studies carried out during the M. Tech. program, both using the CMOS VDTA as the reference architecture and then explore circuit modifications at the input transconductance stage. In the first study, FGMOS devices are introduced to exploit the capacitive gate coupling and threshold voltage modulation. Then, partial positive feedback is subsequently employed to enhance the effective transconductance. In the second study, a series parallel current mirror is incorporated to further boost transconductance while preserving the low-voltage benefits of the FGMOS-based structure. All circuits are simulated in 180 nm CMOS technology using LTspice under identical supply and biasing conditions to ensure a fair comparison. The simulation results show that the conventional CMOS VDTA provides a transconductance of 1.27 mS with a bandwidth of 405.7 MHz, whereas the FGMOS-based realization supports low-voltage operation and exhibits modified frequency behaviour with a bandwidth improvement. The PPF-enhanced design increases transconductance to 1.84 mS with a bandwidth reduction to 148 MHz, while the SPCM-enhanced implementation achieves the highest transconductance of 4.23 mS, with bandwidth of 126.3 MHz. Overall, the findings demonstrate that FGMOS-based VDTA architectures are effective for low-voltage analog design, while PPF and SPCM techniques offer significant transconductance boost with the expected gain-bandwidth trade-off.