SMART ECO FILL FOR FASTER DESIGN CYCLE AND DFM AT DEEP SUB-MICRON TECHNOLOGY

Abstract

One of the driving factors in the semiconductor industry is technology scaling, while technology scaling is enabling the higher number of devices in smaller area by shrinking devices. The continuous growth in transistor integration has significantly improved chip capability and functionality within compact silicon area. However, scaling down metal interconnect dimensions introduces several manufacturing and reliability challenges, requiring additional process optimization and layout-aware fabrication techniques, leading to increasing complexity in the processes being used and also posing the challenges in increased design rules (Design rules check - DRC) and design for manufacturability (DFM) requirements for better yield. [5] The DFM process/data includes two major steps, first is with adding special cells to the design to meet the density of diffusion and poly and secondly with dummy metal insertion in the design to meet the metal density. [5] The DRC and DFM complexity are growing exponentially as we are moving towards deep submicron technologies. Hence, design convergence time for DRC and DFM is also going higher. This is resulting in larger time taken for DRC and DFM convergence compared to earlier technology nodes, which means the above process needs to start much earlier in the design cycle than previous process generation. Taking more time for LV convergence reduces the time available for late ECOs which are due to bug fixes, timing, noise, power and other design fixes. The current ECO implementation tools cannot handle design with DFM. Designers need to remove the DFM data to implement late ECOs and then re-insert the DFM data and then post – DFM DRC cleaning is required. This adds to the overall schedule and large effort for each ECO cycle. Hence there is a need for tool/flow/methodology which can help in implementing ECOs post DFM, thereby reducing schedule impact due to late ECOs. The aim of the project is to provide the design/tool/methodology solution to the problem described above and enable taking in late ECOs in design without affecting schedule.