HYBRID DEEP LEARNING BASED TIMING CHARACTERIZATION OF STANDARD CELL USING SLEW AND LOAD VARIATIONS

Abstract

This study presents a deep learning-based framework for delay modeling and optimization of CMOS combinational logic circuits under varying load capacitance and input slew conditions. Multiple models including DNN, CNN, LSTM, Transformer, and a Hybrid Transformer–DNN model are developed to predict propagation delay. Circuit simulation data are preprocessed and used for model training and evaluation. Performance analysis using MAE, RMSE, and R² metrics shows that the proposed hybrid model achieves the best results with MAE = 2.64 ps, RMSE = 3.52 ps, and R² = 0.988, demonstrating improved prediction accuracy and efficient CMOS timing optimization.