NOVEL 13T SRAM CELL DESIGN: IMPROVED NOISE MARGIN & REDUCED DYNAMIC POWER USING 90NM GENERIC PROCESS DESIGN KIT (GPDK)

Abstract

Static Random Access Memory (SRAM) forms the majority structural component of on chip area in modern System-on-Chip (SoC) designs, and the dual problem of managing power consumption while sustaining noise stability has become progressively more acute as process technology pushes deeper into the nanometer regime. At the 90nm node, The physical implications of device scaling, such as: (shorter gate lengths, thinner gate oxides, And lowered supply voltages significantly increase a number of leakage modes like sub threshold current (Isub), gate tunneling ( Ig), GIDL, And drain-induced barrier lowering (DIBL). In this scenario, the use of conventional 6T cells is not sufficient to ensure both read stability and write-ability at the same time without performance trade-offs that are hard to Gate. Selecting the right sizer. This dissertation describes the design and simulation of a new 13T SRAM cell at the 90nm Technology Node, held and validated by an customized and co-operative GPDK. (GPDK) inside Cadence Virtuoso for use in the proposed two-dimensional concurrent GPDK. the architecture is based. Three structural principles a completely decoupled read buffer threshold text that protects playback froma completely decoupled read buffer, pre venting any disturbance to is used to turn off the storage nodes at the time of read access, a series-stacked control transistor(N9) beneath the drive of RWL whose body follows the running RWL to cut off the cell‘s leakage at the read. Path in hold mode, and a write path whose pull-up and pass-gate transistors are cooptimized for fast state transitions in the presence of optimized cell stability. Although the performance vector of the Schmitt Trigger 10T (ST10T) SRAM cell used as the reference for the entire work. A significiant improvement over the 6T baseline in noise margin by means of hysteresis Enhancement, but does exhibit deficiencies that provide the impetus for our current design. Simulation result of typical-to-typical (TT) process corner, 27C, and nominal VDD Show their proposed 13T cell achieves a 83% dynamic power reduction (from 42.19 x 109 nW to 7.17 x 109 nW), a61%improvementinread access time (TRA: 36 ps to 14 ps) a 19.6% improvement in the write access time (TWA: 92 ps to 74 ps) and A 155% improvement iii in RsNM (Read Static Noise Margin: 111.61 mV to 285.254 m V) all at once, with no sacrifices on any metric. These achievements set the. The proposed 13 T cell is also a promising candidate for embedded memory in low-power VLSI and. Mixed-signal systems at the 90nm process node.