DESIGN OF SINGLE CYCLE 32-BIT RISC-V PROCESSOR

Abstract

This project focuses on the design and implementation of single cycle risc v processor. This project focuses on the design, simulation, and synthesis of a Single-Cycle RISC V Processor using Verilog Hardware Description Language (HDL). The processor is built around the RV32I base integer instruction set, which offers a minimalist yet powerful set of instructions suitable for educational, experimental, and lightweight embedded systems. By implementing the processor in a single-cycle format, all major operations are completed in one clock cycle, simplifying the control logic and providing a clear and effective understanding of the instruction execution process. The architecture follows a modular and systematic approach, comprising five primary stages of instruction execution: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each module is designed to operate synchronously within a single clock cycle, enabling fast and predictable execution. This approach highlights the fundamental working of a processor pipeline in its most basic form, making it ideal for understanding the internal working of modern processors. The design has been developed and simulated using Verilog testbenches to verify the correct execution of various RISC-V instructions, including arithmetic, logical, load/store, and branch operations. Simulation results confirm that the processor accurately handles instruction flow and data processing in accordance with the RISC V ISA specifications. In addition to the 32-bit single-cycle processor, a 64-bit RISC-V processor architecture was also implemented to extend the computational capability of the design. The 64-bit core supports a wider data path and enhanced processing performance while integrating Level-1 (L1) Instruction Cache and Level-1 Data Cache within the architecture. The inclusion of L1 caches significantly improves memory access efficiency by reducing memory principle latency and enabling faster instruction and data retrieval. The cache subsystem was integrated with the processor datapath and memory interface to optimize overall system performance Overall, the project demonstrates the complete development flow of RISC-V processor design, including architecture planning, Verilog implementation, simulation, and hardware verification and Synthesis. The work provides a strong understanding of processor internals, cache integration, and RISC-V architecture with ASIC flow implementation.