ANALYSIS OF LOW-POWER 2:1 MULTIPLEXERUSING DMLANDLDMLTECHNIQUES

Abstract

Power leakage problem has become a challenging issue for modern CMOS digital logic circuits as it becomes more significant in deep-submicron technology due to sub-threshold currents. Here, a low power 2:1 multiplexer circuit is developed using the novel combination of two methodologies viz. Dual Mode Logic (DML) and LEC TOR Dual Mode Logic (LDML). The basic concept of DML involves use of one MODE signal to switch a circuit between two modes namely low power static mode and fast dy namic mode. However, the LDMLtechnique uses leakage control transistors of LECTOR method in combination with DML such that there will always be one transistor operating in its cutoff state independent of any input pattern. Both designs were realized and ana lyzed using LTspice by taking PTM library for 90nm and 45nm CMOS processes with a supply voltage of 1.2 V. The results have shown that LDML Type A consumes the least power of 246.1nW and power-delay product (PDP) is 4.52fJ in 90nmtechnology—about ∼99%power savings compared to DML. 2:1 Multiplexer is one of the most common combinational modules found in processors, memory controllers, communication chips, and many other digital devices. Subthreshold leakage, defined as the current that flows through an OFF-state transistor, has become the main power dissipation factor when the gate channel lengths are less than 50nm and can contribute 30–50%oftheoverall power consumption in standby or inactive conditions. The traditional solutions, like transistor stacking that uses the body effect to minimize leakage, cannot be employed anymore due to increased gate-oxide tunneling at advanced technology nodes. This paper starts by analyzing the basic structure of 2:1 Multiplexer based on NAND and NOT gates in conventional CMOS technology and then gradually applies the LECTOR (LEakage Control TransistOR) mechanism, Dual Mode Logic (DML) and their combination (LDML) to improve power dissipation, propagation delay, and Power-Delay Product (PDP). It was experimentally demonstrated that the most efficient design from all variants examined is LDML Type A which exhibits more than two orders of magnitude lower PDP than domino logic floor documented in scientific literature for both 90 nm and 45nm process technologies