DESIGN OF TERNARY FULL ADDER AND COMPARATOR USING GAA-CNTFET

Abstract

Further advancements in semiconductor technology scaling and the increased need for fast and low-power consumption VLSI systems have led many scientists to consider multi-valued logic and nanoelectronics. Several types of multi-valued systems are available, but ternary logic has shown improved efficiency, decreased complexity, and better representation of data than binary logic systems. In this study, ternary comparators and ternary full adders are designed by employing gate-all-around carbon nanotube field-effect transistors (GAA-CNTFETs) at a 10 nm technology node. This study employs PTL logic, unary operators, and ternary standard logic gates to design the proposed circuits. Owing to its excellent electrostatic characteristics, low leakage currents, enhanced switching, and better carrier transport characteristics, the GAA-CNTFET device structure is highly preferred over the conventional MOSFET and FinFET structures. Ternary standard logic gates, such as STAND, STOR, STNAND, STNOR, and STXOR, and unary operators, such as STI, NTI, and PTI, are implemented to perform arithmetic and comparison operations. The ternary full adder produces effective sum and carry operations through ternary logic values, whereas the ternary comparator performs A>B, A<B, and A=B through CNTFET switching paths. The proposed designs were simulated using the Stanford VS-CNTFET Verilog-A model in the Cadence Virtuoso simulator. The simulation results show that the proposed designs have lower power consumption, less complexity, better switching characteristics, and efficient ternary operations. The results indicate that the proposed GAA-CNTFET ternary system is ideal for low-power nanoelectronics and multivalued VLSI applications.