TCAD-BASED PERFORMANCE ANALYSIS AND OPTIMISATION OF QUADRUPLE-CHANNEL GERMANIUM STEP-FinFETs WITH TRIPLE-MATERIALGATE ENGINEERING

Abstract

The aggressive scaling of the semiconductor devices in the sub-30 nm domain requires new architectural and materials solutions to counter the strong short-channel effects (SCEs) while maintaining high drive currents. This dissertation presents a detailed TCAD study on a novel quadruple-channel Germanium step-FinFET with dual-layer SiO2/HfO2 gate dielectric and Triple-Material Gate (TMG) engineering on Silicon-on Insulator (SOI) substrate. The physical rationale behind the design couples the high carrier mobility of Germanium to the volumetric efficiency of a multi-fin structure . The geometric asymmetry of the step-fin profile optimises ON-state drive and OFF state leakage independently . Furthermore, the TMG structure generates a stepped surface potential along the channel, which decouples the source from the drain potential variations and enhances the carrier transit velocity. The proposed device demonstrates a subthreshold swing of 61.54 mV/dec and a Drain Induced Barrier Lowering (DIBL) of 15.65 mV/V at the gate length of 25 nm with the Sentaurus Device simulations with advanced models for quantum confinement, band to-band tunnelling and surface scattering. The multi-fin Germanium channel exhibits a high maximum transconductance of 18.25 mS/µm and an ON/OFF current ratio larger than 107. Systematic evaluation against silicon-based, single-fin, and uniform-gate benchmarks confirms that the integrated optimization of these four elements delivers short-channel and analog performance metrics that substantially exceed those achievable by any single architectural strategy in isolation. The results establish the proposed device as a very promising candidate for next generation low power high frequency analog and digital applications.