NOVEL SIGNAL-FEED THROUGH FLIP-FLOP OPERATION WITH LOW POWER CONSUMPTION AND HIGH SPEED

Abstract

The paper gives an in-depth analysis of four different pulse-triggered flip-flop (PTFF) architectures, each distinguished by the inclusion of an explicit pulse generation system. The architectures explored are ep-DCOFF, CDFF, SCDFF, and SFTFF, each having various architectural innovations as well as functional advantages. Of particular interest are the inclusion of a conditional discharge method within the CDFF and SCDFF architectures, which successfully overcomes issues of high internal switching activity, output glitches, and input-to-output propagation delays. These enhancements facilitate better energy efficiency and signal integrity in digital circuits. In contrast, the SFTFF presents a new signal feed-through mechanism, which is embedded within a true single- phase clock (TSPC) latch-based architecture. This design feature overcomes the challenge that is inherent with long discharge paths typically found in traditional flip-flop topologies, thus enhancing timing performance as well as power efficiency. The need for low-power and high-speed flip-flop designs is highlighted by the growing need for low-energy electronic systems, specifically in the face of contemporary VLSI (Very-Large- Scale Integration) design. Power dissipation and signal delay are fundamental measures that have a direct impact on the general performance and scalability of integrated circuits. Therefore, the design of proposed PTFFs is key to improving energy-aware digital design. To measure the performance of the suggested flip-flop designs, the research utilizes rigorous simulation techniques with Cadence design tools at the 90nm CMOS technology node. The comparative study shows that the proposed SFTFF design results in a significant power reduction—about 40% less power compared to its counterparts—in addition to reducing transistor numbers. This decrease not only results in reduced energy consumption but also allows for a more densely packed configuration, which is beneficial for high-density integration. Overall, the article emphasizes the key importance of power and delay optimization within flip-flop design and shows that proposed novel SFTFF structure has great potential for future digital systems with low power and high performance.