DESIGN AND PERFORMANCE ANALYSIS OF SAR ADC FOR LOW POWER APPLICATIONS

Abstract

Analog to Digital Converter (ADC) is an important module in the analog front end system that exists between sensors and digital signal processing block. Different architectures of ADCs like Flash, Pipelined, Delta Sigma and Successive Approximation Register (SAR) exist in literature that are utilized for digitization of an analog signal. Moreover, parameters like power consumption, resolution, area, and design cost are considered for the comparison between different existing ADC architectures. Literature indicates that for medium resolution and medium speed applications at low power consumption, SAR ADC is the most suitable choice due to its predominantly digital architecture. In view of these considerations, design of an ultra- low power SAR ADC is undertaken in this research work. A SAR ADC consists of three primary modules: a low-power dynamic comparator, a capacitor- based digital-to-analog converter (CDAC), and a control logic unit that governs the successive approximation process to convert the sampled analog input into its corresponding digital representation. Power consumption of each and every module is required to be reduced so as to reduce the power of complete designed ADC. However, DAC is the most power consuming block in a SAR ADC, design and parametric optimization of each and every module is considered stepwise. First of all, design and parametric simulation analysis of different low power dynamic comparators in CADENCE Virtuoso 45 nm technology node is carried out. In this, Strong arm latch dynamic comparator is considered as the baseline comparator consisting of preamplifier and regeneration latch. This comparator retains the direct path connection between VDD and ground and due to this, the circuit consumes 51.38 nW of average transient power consumption. Further, double tail dynamic comparator and modified double tail dynamic comparator are considered for design, simulation & analysis and the transient analysis of both comparators is focussed. The observed delay, power consumption and kickback noise in these comparators required an architectural improvement in the design of existing comparators. Following this, first proposed dynamic comparator architecture design along with the simulation analysis is focussed. Simulation of first proposed dynamic comparator observed average transient power of 33.81 nW at nn corner which is much reduced value compared to the other architectures like strong arm latch, double tail dynamic and modified double tail dynamic comparator. The power consumption is limited to 19.56 nW at ss corner as the architecture created an isolation between pre-amplifier and latch module when clk is low due to which leakage power is avoided. The vii proposed comparator is simulated with capacitive loading of 5.1 pF which is the required value for utilizing the designed comparator module along with capacitive DAC. PDP of 0.4 fJ along with temperature variation from -40-degree centigrades to 110-degree centigrades is also measured for the first proposed comparator. Further, a dynamic comparator based on charge sharing logic and kickback noise reduction logic is also proposed which is working well for few GS/s and power consumption of 9.36 μW is observed at 1 GS/s. Proposed charge sharing logic based dynamic comparator is limiting offset voltage to 7.8 mV and delay within 48.2 ps. Proposed charge sharing logic-based circuit is less sensitive to Vcm variations as gm/ID of input transistors is enhanced with the biasing of transistors in weak inversion region. The observed delay exhibits a reduction from 56.3 ps to 23.17 ps as the input differential voltage (Vdiff) ranges from 10 mV to 200 mV for varying common-mode voltage levels (Vcm) in the proposed charge sharing dynamic comparator. The comparator demonstrated the reduction in kickback noise by employing auxiliary transistors M8 and M9 (Fig.3.12) to separate the output nodes. Additionally, this approach effectively mitigated the mismatch effect and minimized the impact of parasitic capacitance associated with the transistor design. Further, designing of DAC module with reduced switching energy per conversion step drew attention of researchers in the design of ultra-low power SAR ADC. In literature many DAC switching schemes are implemented by the researchers like common mode switching scheme, monotonic switching scheme, capacitor splitted switching scheme, merged capacitor etc. Each switching scheme followed a different switching methodology and contributed to the saving of switching energy per conversion cycle compared to the conventional one. Traditional switching scheme consume 682.5 CV2ref while 427.66 CV2ref of switching energy is consumed by split capacitor technique. So, there exists a research scope in the design of DAC unit with zero switching energy in the first two MSB comparisons. In view of above, inclusion of single ended topology-based switching scheme for the design of digital to analog converter (DAC) is considered. The proposed switching scheme utilized a single reference voltage of Vref/2 and performed the first two MSB comparisons with zero switching energy. The scheme required average of 57.4 CV2ref of switching energy which is a much-reduced value, approximately reduced by a factor of 92 percent compared to conventional capacitor-based switching scheme. Also, compared to conventional switching scheme, the number of capacitors in the DAC array are reduced by 50 percent. viii In the switching scheme, a single ended behaviour is obtained utilizing a dummy DAC at the positive input of comparator that felicitated first two comparisons without any switching power. Also, after first comparison of Vin with Vref/2, the bottom plate of dummy DAC is switched either to ground or Vref/2 and stayed in that state till the final digitization is performed with Vref value of 1.1 V. Also, for the proposed DAC implementation, MOM capacitors are suggested to be the preferred choice to shift the design from schematic to final back-end stage. Third Module of SAR ADC is the design of a low power control unit. The literature observed the necessity of SAR logic and DAC co-optimization, especially when advanced switching techniques such as monotonic, common-mode (VCM)-based, and capacitor-splitting schemes are employed for switching. Based on the above requirement to design a SAR logic-based control unit with better DAC-logic synchronization and to further reduce nonlinearity in SAR ADC, the design of low power SAR logic-based control unit is considered as further part of the research work. The design of the control unit began with the development of enhanced D flip-flops to improve setup and hold time performance. After this, the clocking system is designed using the main clock along with internally generated clock signals to achieve proper timing synchronization. In the initial stage, multiplexers and sampling logic are implemented to support accurate sampling and signal control. The SAR logic is then generated step by step in a bitwise manner to implement the proposed switching scheme. Finally, by using enhanced D flip-flops and multiplexers with proper synchronization, an improved control unit is developed to successfully implement the proposed switching scheme. Enhanced D flip flop is working well for the required bandwidth and resolution of input signal at low power consumption. The proposed synchronous control unit has less complexity and better timing synchronizations due to which all the control signals are getting generated within time constraints. Sampling phase begins the digitization process when Xs is low and Dp (comparator output) is the digitized output bit which is generating digital data in synchronization with internal generated clock signals (Q1 to Q7) and providing better linearity in the digital data generation process. The control unit implemented the SAR logic in a bitwise manner. After the initial sampling operation triggered by the first clock signal (clkc), the most significant bit (MSB) is resolved. Subsequently, the internal clock signal Q1 provides precise timing synchronization for the generation of the MSB-1 bit. The remaining bits are generated sequentially by the control unit with optimized timing coordination between the DAC and the comparator, thereby improving conversion accuracy. In this process, the internal clock signal Q2 synchronizes the generation of the MSB-2 bit, and the same sequence continued for the ix lower-order bits. The resolved digital bits are stored in a shift register, and based on the clock timing, the stored data is finally read out as an 8-bit digital output of the designed SAR ADC. Proper interfacing of the designed modules along with effective control of the common-mode Vcm is critical for achieving an ultra-low-power SAR ADC. In this work, non-linearities such as differential non-linearity (DNL) and integral non-linearity (INL) are minimized while maintaining low power consumption, in line with observations reported in the literature. The effectiveness of the proposed approach is reflected in the calculated INL and DNL values obtained from the digitized output. Based on these considerations, a fully interfaced 8-bit SAR ADC incorporating all optimized modules is designed. Henceforth, finally, all the designed modules; comparator, DAC & control unit are interfaced to design an 8-bit SAR ADC with single reference voltage Vr/2 based dummy DAC designed along with bootstrap switch to give zero switching energy in first two MSB conversions. The reduced power consumption of the designed 8-bit SAR ADC is limited to the value of 5.38 μW. Parametric simulation analysis shows that SNDR value of 46.08 dB, SFDR 47.89 dB, ENOB 7.38 bits, DNL +0.13/(-0.12) LSB, INL +0.52/(-0.90) LSB at sampling rate of 540 KS/s is obtained. The entire design is simulated in CADENCE 45 nm technology node. The Proposed SAR ADC is completely designed at transistor level implementation of each module including comparator, DAC unit and control logic. The DAC unit consumes zero switching energy in the first two MSB decisions as per proposed switching algorithm which results in the saving of 92 % of switching energy with respect to the conventional switching scheme at 540 KS/s. The research conducted herein shows that the proposed 8-bit SAR ADC is digitizing the analog sampled value in 8 bits with sampling frequency of the order 540 KS/s. The measured parameters validating that power consumption of the designed ADC is limited to 5.38 μW and other parameters like INL, DNL are also within permissible range to confirm the effectiveness of the design for low power sensor applications. The research widens the horizon to include adaptive decision algorithms in the design that can help mitigate non-idealities such as capacitor mismatch and comparator offset in further research.