STUDY AND DESIGN OF LOW LEAKAGE NANOWIRE FIELD EFFECT TRANSISTOR

Abstract

The continuous downscaling of semiconductor devices, as predicted by the Moore’s law, has significantly improved computational capability, power efficiency and integration density over the past five decades. However, with the transition into the deep sub-nanometer regime, conventional CMOS technology has encountered formidable challenges such as increased leakage currents, degraded subthreshold swing, escalating power dissipation and short channel effects (SCEs). The inability of traditional transistor architectures to maintain electrostatic integrity at reduced dimensions has motivated the exploration of novel device geometries and materials capable of sustaining high performance while ensuring low-power operation. In this context, the present research investigates the design, modelling and performance evaluation of advanced nanowire field effect transistors (FETs) that combine dielectric, ferroelectric and electrostatic engineering to overcome the limitations of conventional MOSFETs. The study is centred on the progressive development of five distinct nanowire FET architectures, each addressing specific challenges of device scaling through geometric and material innovation. The overarching objective of this work is to achieve superior gate controllability, enhanced current drivability and reduced subthreshold swing, thereby paving the way for energyefficient transistors suitable for next-generation nanoelectronics applications. The initial part of the research presents the Double Metal Gate Macaroni Nanowire Field Effect Transistor (DMGM-NFET), where two metals with different work functions are used within the gate stack to modulate the channel potential. This configuration enables a stepwise potential distribution that effectively reduces gate induced drain leakage (GIDL) and drain induced barrier lowering (DIBL). The macaroni type hollow nanowire geometry further enhances gate coupling, allowing improved electrostatic control over the channel region. Simulation results confirm a substantial improvement in subthreshold swing and ON/OFF current ratio when compared to the conventional FETs. This device establishes the foundation for electrostatic optimization through multi metal gating. Building upon this concept, the study extends to the Hetero-Dielectric Macaroni Channel Cylindrical Gate All Around Field Effect Transistor (HD-MC CGAA FET), which employs a dual-dielectric gate stack consisting of high-κ (HfO2) and low-κ (SiO2) materials. The heterogeneous dielectric configuration redistributes the gate electric field, enhancing potential control near the source end while minimizing fringing field effects at the drain. This selective field enhancement results in reduced subthreshold slope and improved channel confinement. Comparative analysis with single-dielectric and single-metal counterparts demonstrates that the hero-dielectric approach yields higher transconductance, improved current and stringer immunity to short channel effects. These findings confirm that dielectric heterogeneity, combined with cylindrical symmetry, can significantly improve device performance at nanoscale dimensions. xi The research then transistors from electrostatic to material-based innovation through the incorporation of ferroelectric materials in the gate stack. The Negative Capacitance Nanowire FET (NC-NW FET) introduces a ferroelectric HfZrO2 layer in series with a high-κ dielectric, harnessing the negative capacitance (NC) effect to achieve internal voltage amplification. This phenomenon allows the device to operate with a subthreshold swing below the Boltzmann limit of 60 mV/decade, leading to lower operating voltages and energy efficient switching. The simulation analysis confirms a marked reduction in power dissipation and a significant improvement in drive current. Furthermore, the hysteresis behaviour is optimized through careful tuning of the ferroelectric layer thickness and capacitance matching with the underlying dielectric stack. The results validate that ferroelectric integration can effectively address the fundamental trade-off between switching speed and power consumption in nanoscale transistors. To further enhance device controllability and eliminate residual instability, the work explores cylindrical ferroelectric architectures, resulting in the Cylindrical Ferroelectric Dual Metal Nanowire FET (C-FE-DM-NW FET). This design combines the advantages of dual metal configuration allows precise control of the potential barrier near the source and drain, while the ferroelectric layer enhances surface potential modulation through polarization-driven voltage amplification. The resulting device exhibits a subthreshold swing below 55 mV/decade, negligible DIBL, and an ON/OFF current ration in the range of 108 -109 , confirming excellent electrostatic integrity. Moreover, the transconductance and drain current are significantly improved, validating that the synergy of dual-metal and ferroelectric gate engineering is crucial for achieving both steep-slope and high-drive devices. The final and most advanced device proposed in this work is the Cylindrical Gate Engineered Ferroelectric Nanowire FET (CGEF-NW FET). This architecture introduces gate-length partitioning and optimized ferroelectric layer placement within the cylindrical structure to achieve near-ideal electrostatic control and hysteresis free operation. The CGEF-NW FET demonstrates an exceptionally low subthreshold swing of approximately 50 mV/decade, a high ON/OFF current ratio exceeding 109 , and minimal power dissipation. The optimization of gate geometry and ferroelectric parameters allows superior potential modulation while maintaining capacitance stability, thereby providing the most balanced performance among all proposed designs. The CGEF-NW FET thus represents the culmination of this research efforts combining geometry, field and material engineering to achieve a scalable and energy efficient transistor for sub-5 nm technology nodes. A comprehensive comparative analysis among all the proposed devices illustrates a clear performance improvement trend: the subthreshold swing decreases from approximately 70 mV/decade in the DMGM-NFET to nearly 50 mV/decade in CGEF-NW FET, while the ON/OFF current ratio increases by more than three orders of magnitude. The DIBL is reduced to nearly negligible levels in ferroelectric devices, and the drain current performance is significantly enhanced. These improvements are attributed to the synergistic interplay between electrostatic optimization, dielectric engineering and ferroelectrics voltage amplification, confirming that the strategic integration of these techniques can collectively surpass the scaling limitations of xii conventional CMOS transistors. The thesis also discusses the future research prospects and practical realization pathways for the proposed devices. Experimental fabrication using Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD) is recommended for producing high-quality HfO2 and HfZrO2 films with nanometre-scale precision. Structural and phase characterization through Transmission Electron Microscopy (TEM) and X0Ray Diffraction (XRD) will enable validation of the simulated results, while Piezo response Force Microscopy (PFM) can be employed to verify ferroelectric polarization and stability. Further optimization of doped ferroelectric materials could improve endurance and minimize coercive voltage, making these designs more robust for integrated circuit applications. The proposed devices are also highly promising for circuit-level and systemlevel integration, particularly in low-power digital logic, non-volatile memory and neuromorphic computing architectures. Their ability to operate at low supply voltages and high switching speeds positions them as potential enablers for energy-efficient processors, artificial intelligence hardware, and edge computing systems. Additionally, due to their low energy consumption and compact footprint, these devices could be extended to flexible electronics and biomedical sensor platforms, paving the way for green and sustainable nanoelectronics systems. From a broader perspective, the innovations presented in this thesis hold substantial technological and societal impact. By significantly reducing the power requirements of electronic systems, the proposed nanowire FETs contribute to global efforts toward energy conservation and sustainable electronics manufacturing. Their compatibility with existing CMOS fabrication processes ensures a practical transition path for semiconductor industries towards post-CMOS device paradigms. Furthermore, the reduction in energy consumption directly aligns with global objectives such as carbon footprint minimization and sustainable digital transformation. In conclusion, this thesis provides a comprehensive and systematic exploration of next-generation nanowire transistor architectures that transcend conventional scaling barriers through a combination of electrostatic design and ferroelectric innovation. The research demonstrates that by co-optimizing gate geometry, dielectric heterogeneity, and ferroelectric polarization, it is possible to achieve sub thermal switching, low leakage, and exceptional electrostatic control all within a CMOS compatible framework. The proposed devices collectively form a technologically feasible and environmentally sustainable foundation for the development of ultrascaled, low power, and high-performance electronics in the post-CMOS era. This work not only advances the scientific understanding of ferroelectric and nanowire device physics but also contributes meaningfully to the realization of energyefficient semiconductor technologies that align with both industrial evolution and societal responsibility.