DESIGN AND DEVELOPMENT OF STRAINED CHANNEL ENGINEERED MULTIGATE FERROELECTRIC BASED FINFET FOR ANALOG AND CIRCUIT APPLICATIONS

Abstract

The growing demand for low-power, high-performance electronics, smart devices, and logic-inmemory systems has pushed Complementary Metal Oxide Semiconductor (CMOS) scaling to its physical limits, where challenges such as gate leakage, Drain Induced Barrier Lowering (DIBL), and dopant variability hinder further advancements. Ferroelectric FinFETs (FeFinFETs) address these issues by integrating ferroelectric materials with FinFETs, enabling strong electrostatic control and polarization-driven charge modulation to suppress short channel effects (SCEs) and enhance device performance. Building on this, the present work investigates a strained Vertically Stacked FeFinFET (VS-FeFinFET) architecture, incorporating silicon on insulator (SOI) based substrate engineering to improve energy efficiency and reduce parasitics, and strained Si/SiGe heterostructure tri-layered channel system for enhancing carrier transport. These combined strategies culminate in the development of the Vertically Stacked Heterostructure on Insulator FeFinFET (VS-HOIFeFinFET), offering superior scalability and robust device performance for next-generation modern applications. Initially, the extensive analysis is done to optimize VS-HOI-FeFinFET and on comparison with baseline FeFinFET, VS-HOI-FeFinFET is found to show remarkable improvements in terms of various measured parameters such as 97.84% reduction in leakage current (Iof f ) and 35.98% increment in drain current (Ion), which consequently results the switching ratio to increase around 61 times along with substantial improvement in threshold voltage and subthreshold swing. Further, four multi-material gate stack configurations such as C1(SiO2+Al2O3), C2(SiO2+HfO2), C3(Al2O3), ix KAJAL VERMA and C4(Al2O3+HfO2), are analysed and with the sequential enhancement in static and analog performance, C4 showcased upto 5 times improvement in switching ratio, ∼41% reduction in DIBL, and ∼58% better quality factor along with achieving remarkable improvements in early voltage, intrinsic gain, device efficiency, output resistance, and conductance, highlighting suitability for analog applications. In addition, the optimization with variation in mole fraction, fin geometry and oxide-ferroelectric layer thickness is proved as critical levers for tuning the electrostatics of the device to achieve lower leakage, improved switching ratio and enhanced gate control, thereby ensuring energy-efficient, reliable, and scalable device design for improved performance. RF analysis revealed three times improvement in gain frequency product (GFP) and gain transconductance frequency product (GTFP), along with 16% reduction in unity gain cut-off frequency, enabling high-frequency amplification with minimized noise distortion. Collectively, these optimizations provide a robust design strategy for achieving energy-efficient, reliable, and high-performance FeFinFET tailored for future high performance analog and RF applications. Furthermore, VS-FeFinFET is explored for improved reliability under the influence of interfacial trap charges (ITCs) at the semiconductor/oxide interface. Gate engineering has also been incorporated to form hetero dielectric vertically stacked ferroelectric based FinFET (HD-VS-FeFinFET), which results to 91.48% reduction in Iof f and 13 times increment in switching ratio along with improvement in quality factor by 46.01%, transconductance (gm) by 32.77%, and device efficiency (TGF) by 26.54% with negligible variations due to ITCs as compared to VS-FeFinFET. Various linearity and harmonic parameters also improved and showed negligible average variations like 4.72% (177.15%) in VIP2 and 6.52% (25.3%) in 1-dB compression point for HD-VS-FeFinFET (VS-FeFinFET) against different ITCs polarity making it more reliable for low power microwave and distortionless wireless communication applications. Further, logic circuit application of HDVS-FeFinFET based CMOS inverter has been analysed and it shows improvement by 17.9% in transition range, 51.67% in voltage gain along with minimal ITCs induced average variation of 3.66% (15.88%) in noise margin for HD-VS-FeFinFET(VS-FeFinFET) based circuit, showcasing its enhanced reliability at circuit level. Thereafter, a detailed investigation is carried out to analyse the coupled effects of thermal-trap dynamics on the performance of HD-VS-FeFinFET device along with enhancing its applicability as CMOS inverter in varying operating environments. Temperature affectability reveals that HDx Delhi Technological University, Delhi-42 KAJAL VERMA VS-FeFinFET exhibits better reliability with less average variations against ITCs at all operating temperatures such as 10.65% in Iof f and 11.39% in output resistance (Rout) at 300K which further decreases to 8.13% in Iof f and 7.76% in Rout at 400K in contrast to huge variation shown by VSFeFinFET like 82.05% in Iof f and 43.10% in Rout at 300K along with 59.35% in Iof f and 29.86% in Rout at 400K. Further, the analysis done at various ITCs densities and polarities reveals that, at higher donor trap charge density of 1013 cm−2 , the device performance alters significantly for VS-FeFinFET with degradation in Iof f by 552 times in comparison to HD-VS-FeFinFET which degrades only by 2.52 times, thus making it more reliable under varying environmental conditions. Subsequently, HD-VS-FeFinFET based CMOS inverter demonstrates high reliability and robustness under combined effects of temperature variation and ITCs with only 6.8% reduction in noise margin when temperature rises from 300K to 400K along with negligible variations at all operating temperatures, exhibiting its improved immunity against ITCs, making it a reliable choice for digital circuits in varying operating environments. Later, a comprehensive investigation of ferroelectric HfO2 based devices is presented, encompassing both material-level and device-level analyses. At the device level, the impact of various doped ferroelectric materials on the transfer characteristics of HD-VS-FeFinFET is studied, highlighting dopant-driven modulation of the performance parameters with enhancement in Ion by 24%, gm by 29% and TGF by 10.8% for silicon doped HfO2 over lanthanum doped HfO2 as ferroelectric layer. Subsequently, Density Functional Theory (DFT) simulations are performed to examine the structural and electronic properties of undoped HfO2 and its doped variants using Gadolinium (Gd) and Silicon (Si), which are found to be two best performing ferroelectric materials at the device level. The influence of different dopants material on band structure and projected density of states are analyzed to evaluate their suitability for ferroelectric applications. The influence of increasing dopants concentration for silicon doped HfO2 is also studied at DFT level. Further, self-heating effects (SHE) are critically examined in HD-VS-FeFinFET structure across varying biasing voltages and ambient temperatures. The analysis reveals influence on analog parameters along with lattice temperature contour evolution due to SHE, emphasizing its impact on device reliability. Further, the output characteristics also show alteration in drain current by 33.3% due to SHE which decreases to 0.03% with reduction in Vgs from 0.6V to 0.2V. Finally, CMOS inverter circuit utilizing these advanced technologies is analyzed in terms of switching characteristics under different biasing xi Delhi Technological University, Delhi-42 KAJAL VERMA voltages and thermal conditions. Key performance metrics such as switching current, propagation delay, rise time, and fall time are also evaluated to assess circuit-level implications of material and device-level effects. Along with this, circuit level analysis of HD-VS-FeFinFET based NAND logic gate circuit is also examined. Thus, the integrated multi-scale analysis provides a holistic understanding of material doping, thermal effects, and circuit performance, establishing a pathway for the optimized design of ferroelectric-based next-generation systems in advanced low-power, high-speed electronic applications. In conclusion, HD-VS-FeFinFET emerges as a highly promising device for next-generation lowpower and high-performance analog and circuit applications. Its remarkable switching ratio, minimal leakage, strong resilience against thermal-trap variations, coupled with superior static, analog, and RF characteristics along with enhanced switching dynamics and improved inverter noise immunity, position it as a robust and energy-efficient solution for future CMOS technologies.