DESIGN AND IMPLEMENTATION OF REVERSIBLE LOGIC GATES AND ITS APPLICATION IN EMERGING TECHNOLOGIES

Abstract

The increasing demand for high-speed, low-power, and scalable computing architectures has driven significant interest in reversible logic and all-optical computation. Conventional irreversible electronic systems inherently dissipate energy due to information loss, while photonic technologies offer ultra-fast signal propagation and immunity to electromagnetic interference. Reversible logic, when combined with optical implementations, provides a promising pathway toward energy-aware, quantum-compatible, and high-throughput computing systems. This thesis presents a comprehensive investigation into the design, modeling, and realization of reversible arithmetic and logic circuits for fixed-point unsigned integer data, with a primary focus on quantum and all-optical architectures. The work begins with the design of a reversible 4×4-bit Vedic multiplier based on the Urdhva– Tiryagbhyam (UT) algorithm, constructed using two proposed 2×2 Vedic multiplier modules and newly developed reversible ripple-carry adder (RCA) and carry-save adder (CSA) circuits. The proposed 4-bit Vedic multiplier is analytically compared with state-of-the-art reversible designs and is shown to be superior in terms of quantum cost (QC), gate count (GC), hardware complexity (HC), ancilla inputs (AI), and garbage outputs (GO). Logical correctness is verified using Xilinx Vivado, and an entropy-based analysis confirms the energy-saving benefits of reversibility by demonstrating reduced information loss. Building on this optimized real multiplier, the architecture is extended to realize a reversible complex Vedic multiplier in the quantum domain, following a modular and scalable design methodology. The thesis then explores all-optical N-bit Vedic multipliers based on MZI–SOA interferometric switches, constructed using existing optical adder architectures. These designs are analytically benchmarked against prior optical multipliers in terms of optical cost (OC) and optical delay (OD), and closed-form expressions for N-bit OC and OD are derived. The analysis reveals inherent scalability and stability limitations of interferometer-based designs due to phase sensitivity, interferometer duplication, and irreversibility. To overcome these challenges, interferometer-free RSOA-based reversible optical architectures are proposed. A family of RSOA-based reversible logic gates and arithmetic blocks is developed using cross-gain modulation (XGM). Using these primitives, scalable N- vi bit reversible Vedic multipliers are formulated analytically, and expressions for OC, OD, constant inputs (CI), and garbage outputs (GO) are derived. A key contribution of the optical domain is the design of a parity-preserving 2×2-bit reversible optical Vedic multiplier, implemented using RSOA-based logic gates. This multiplier is photonic-level simulated, and its performance is quantitatively evaluated using Extinction Ratio (ER), Q-factor, and Relative Eye Opening Percentage (REOP). Comparative analysis with existing optical multipliers demonstrates superior signal integrity and fault-awareness. This parity-preserving 2-bit building block is then extended analytically to construct an N-bit complex Vedic multiplier, with closed-form expressions derived for OC, OD, CI, and GO. Additionally, the thesis introduces a novel universal reversible NAND–NOR gate (NTG) realized using a hybrid RSOA and MZI–SOA switching mechanism, capable of implementing all fundamental Boolean logic functions and serving as a universal primitive for reversible optical logic synthesis. The final part of the thesis develops a reversible RSOA-based universal multiplexer framework, including 2×1 and 4×1 multiplexers, and demonstrates how these structures can realize all basic logic functions (AND, OR, NOT, XOR, XNOR, NAND, NOR) as well as half- adder and half-subtractor circuits. Performance evaluation based on Contrast Ratio (CR), Extinction Ratio (ER), and Relative Eye Opening Percentage (REOP) confirms the superior signal quality, robustness, and integration potential of the proposed RSOA–FRG architecture compared to existing photonic logic designs. Overall, this thesis establishes a unified, modular, and scalable methodology for reversible arithmetic and logic circuit design across quantum and photonic domains. The proposed architectures demonstrate strong potential for energy-efficient, fault-tolerant, and high-speed computation, providing a solid foundation for future extensions toward floating-point arithmetic, sequential reversible circuits, and large-scale integrated optical and quantum computing systems.