DESIGN AND COMPARATIVE ANALYSIS OF A DIFFERENT FULL ADDERS FOR LOW POWER AND HIGH-SPEED VLSI APPLICATIONS ACROSS TECHNOLOGY NODES

Abstract

With the continued scaling of CMOS technology into deep submicron regions, achiev- ing a balance between low power consumption and high-speed operation has become essential in digital arithmetic units. The full adder, a fundamental building block in arithmetic logic units (ALUs), has been widely studied to reduce power, delay, and area metrics. Traditional 28-transistor (28T) and 14-transistor (14T) full adder designs offer robust performance but suffer from excessive power consumption and large layout area at advanced nodes. This thesis presents the design, implementation, and comparative analysis of three compact 10-transistor (10T) full adder architectures—CMOS-based, SERF-based (Static Energy Recovery Full Adder), and GDI-based (Gate Diffusion Input)—across 180nm, 90nm, and 45nm CMOS technology nodes using Cadence Virtuoso. These designs were evaluated for average power consumption, propagation delay, power-delay product (PDP), and layout area. Simulation results show that the 10T SERF adder achieves the lowest PDP (110.20 fJ) and fastest delay (54.8ps at 45nm), while the 10T GDI design consumes the least power (1.89μW at 45nm) and offers the smallest area. In comparison to conventional 14T and 28T architectures, the proposed 10T designs consistently demonstrate superior energy efficiency, reduced area, and improved scalability, making them suitable for next- generation low-power and high-speed digital systems.