DESIGN AND ANALYSIS OF SRAM CELLS UNDER STABILITY, POWER AND SPEED CONSTRAINTS

Abstract

Memory plays a vital role in most of the electronic devices used in embedded systems. The increasing processing workload has led to a growing demand for low-power, high- performance SRAM cells. The memories are formed by an array of SRAM cells for data storage and their peripheral circuits. The peripheral circuit comprises row-column decoders and pre-charge circuitry. The 6T SRAM cell was the industry standard, but with decreasing technology node and VDD scaling, the performance of the 6T SRAM cell was deteriorating. This has motivated researchers to design other SRAM cells. SRAM cells play a crucial role in the design of system-on-chips (SoCs), constituting a substantial portion of the die area and thereby contributing to increased power consumption. Despite significant advancements in SRAM performance in finer technologies, concerns persist regarding cell stability in the deep sub-micron domain. This thesis introduces an innovative approach to address these issues by proposing a low- power SRAM cell based on swing restoration inverter (SRI). The swing restoration inverter (SRI) addresses the challenge of swing voltages in finer technologies by integrating two additional transistors to act as swing-restored elements. This innovation results in an impressive 67% reduction in leakage power at 27°C for the 90 nm technology. To evaluate the effectiveness of the proposed SRI-based SRAM cell, performance metrics such as delay and power delay product are calculated. In the context of a 6T SRAM cell in the 90 nm technology, the conventional inverters are replaced with the swing restoration inverter (SRI). The implementation of SRI in the proposed 8T SRAM cell leads to a substantial 86% reduction in leakage power at 108°C and an impressive 91.22% reduction at 27°C compared to the conventional 6T SRAM cell. The SRI technique proves instrumental in enhancing stability, resulting in the proposed 8T SRAM cell outperforming its 6T SRAM counterpart. However, it's important to note that the heightened performance of the proposed 8T SRAM cell comes at the expense of two additional transistors. Simulations are conducted using the 90 nm technology and the Cadence Virtuoso simulator to validate the effectiveness of the swing restoration inverter (SRI) technique in leakage power consumption and enhancing stability in SRAM cells. This thesis examines the factors that affect the Static Noise Margin (SNM) of Static random-access memories. Find the equivalent time, improve hold, read, and write operation of the low power 8T SRAM cell, which is better than 6T SRAM and standard v 8T SRAM cells using swing restoration dual node voltages for hold, read, and write operation, and improve stability analysis. This circuit or architecture-level SRAM technique is required to improve hold, read, and write SNM. This thesis, comparative analysis of 6T SRAM, standard 8T SRAM, and low power 8T SRAM cells with improved read and write noise margin, is completed for nanometer technology. The typical memory for very large-scale integrated (VLSI) circuits has traditionally been static random-access memory (SRAM) because it has offered faster speeds compared to other alternatives. However, SRAM has been associated with a high-power consumption rate. Researchers have recognized the importance of lowering the power consumption of SRAM cells due to their critical role in memory architecture. This literature review has aimed to provide innovative and effective strategies for designing low-power SRAM cells. Several circuit topologies and methodologies have been introduced to compute stability, leakage current, delay, and power, and novel techniques for designing SRAM cells based on eight transistors (8T) have been proposed. SRAM has frequently been chosen over dynamic random-access memory (DRAM) because it has demonstrated faster speeds and lower power consumption. It has been named "static" because no modification or action, such as refreshing, has been required to maintain data intact. However, leakage current in SRAM has often increased and impaired its performance as technology nodes have been scaled down. Voltage scaling has been adopted as a solution to this issue, although it has also affected the stability and latency of SRAM. A separate (isolated) read port has been employed to enhance read stability, while a negative bit-line (NBL) write- aid circuit has been implemented to improve write ability. The proposed design has been evaluated against cutting-edge approaches based on criteria such as write static noise margin (WSNM), write stability, read static noise margin (RSNM), and other performance metrics. Future research has been directed toward exploring novel circuit topologies and methodologies to further enhance stability, reduce leakage current, and minimize delay and power consumption. Researchers have also investigated the performance of SRAM cells at smaller technology nodes to develop new techniques for maintaining stability and performance at these scales. Additional efforts have been made to explore new approaches to voltage scaling and to develop methods that improve the read and write stabilities of SRAM cells. vi In this thesis, we introduce a proposed 8T SRAM cell that incorporates an isolated read path to enhance read stability compared to the conventional 6T SRAM cell. To address leakage power, two PMOS transistors are integrated into the read and write circuitry, effectively minimizing leakage current induced by stacking effects. The proposed 8T SRAM cell design demonstrates a substantial reduction in leakage current, exhibiting a decrease of 61.11% compared to the 6T SRAM cells, respectively. Moreover, the read operation for the newly proposed 8T SRAM cell is significantly improved, showcasing a 53.08% improvement compared to the 6T SRAM cell, respectively. The results also indicate noteworthy speed enhancements during write operations, boasting a 66.66% improvement compared to the 6T and 8T SRAM cells, respectively. The Read Static Noise Margin (RSNM) and write trip point (WTP) of the proposed cell measure at 12 mV and 360 mV, respectively, signifying an improvement over the conventional 6T SRAM cell measures at 6.37 mV and 240 mV. The effectiveness of the proposed cell is validated through comprehensive simulation analyses conducted in the Cadence Virtuoso environment at the 90 nm technology node. All the proposed cells are of a double-ended nature owing to their better performance at lower power and high speed. This growing demand for double-ended cells has also generated the need for a swing restoration inverter (SRI) and negative bit line (NBL) circuits that are compatible with the array of double-ended SRAM cells. Conventionally, sense amplifiers were designed with differential SRAM cells. These SRAM cells are usually voltage-based in nature, owing to their low power and high speed with low operational VDD. Thus, this generates a need for double-ended SRAM cells that have low power consumption