HIGH PERFORMANCE SRAM DESIGN

Abstract

Static random access memory (SRAM) is a crucial component of computer systems that uses a significant amount of space and power. Reliable SRAM with high density and low power consumption is ideal for portable devices. Today, low-power applications includ- ing wireless sensor networks, implanted biomedical devices, and other battery powered portable devices need SRAM with a smaller footprint and lower power consumption. Supply voltage (VDD) scaling is one of the widely used methods to reduce leakage and dynamic power. However, the design of SRAM at lower operating voltages is severely hampered by the greater diversity in contemporary scaling technology. SRAM perfor- mance and reliability have been compromised as a result of significant read and write errors caused by increased leakage power and manufacturing variability as the device size continues to shrink down. For a long time, the conventional 6T SRAM cell has been the industry standard. However, due to its deteriorated read static noise margin (RSNM), the 6T SRAM cell is suscepti- ble to continual read upsets even when it is operating at low VDD. Similarly, the 6T cell may not be able to reverse the stored data and may experience frequent write failures due to its inability to reliably maintain the device strength ratio at lower supply voltages. Numerous solutions have been put out in the literature to get around the drawbacks of the conventional 6T SRAM cell. Nevertheless, due to their dual bitline (BL) construction, differential cells show quite high dynamic power consumption despite all of their advance- ments. The use of single-ended structures may seem to be the most effective method of lowering dynamic power consumption because single-ended cells have a reduced bitline switching activity factor. As a result, single-ended cells are becoming more and more prevalent in an effort to lower overall power consumption. A single BL SRAM design that leverages single-ended read/write operations is first presented. It uses Schmitt-trigger (ST) inverter and power gating approach, to improve read and write performances. The proposed design exhibited lower power consumption, reduced delay, and improved stabil- ity. The single BL structure with stacking effect lowers the proposed design leakage and dynamic power consumption. At lower technology nodes, the SRAM cell is more vulnerable to soft errors. Multi- bit soft errors/upsets (MCUs) have become a greater threat to the stability of SRAMs in vii ultrascaled technology because of the reduced effective space between transistors. To ad- dress this problem, the bit interleaving (BI) architecture technique is an effective solution. Nonetheless, this method works with cells that are half-select (HS) free in nature. The study proposes an HS disturb-free SRAM design with improved stability, high speed, and low power consumption to address this issue. The proposed design improves soft-error immunity by utilizing a bit-interleaving design. By including a dedicated write chan- nel for ‘1’ and ‘0’ and a power cutoff transistor coupled to virtual ground (VGND), the proposed architecture improves write performance. Utilizing a single bit-line, a stacked transistor, and a smaller bit-line capacitance results in a lower power consumption. The usage of a read decoupled structure contributes more to the read stability of the proposed design. SRAM’s vulnerability to single event upset (SEU) is increased by the modern technol- ogy’s higher transistor integration and scaling cell VDD. A nondestructive, soft-error variant of single-event effects (SEEs) is called a SEU. The minimal distance between transistors is getting smaller as complementary metal oxide semiconductor (CMOS) tech- nology continues to grow. Therefore, in advanced systems, a single particle strike can impact numerous transistors, while only one transistor was usually impacted by earlier technology. In advanced nanometre CMOS technology, charge sharing causes single- event multiple-node upsets (SEMNUs), which are now the most common consequence of intense particle hits. In the vacuum of space, alpha particles and cosmic radiation can cause the node data to be altered, leading to data loss. When a radiation particle hits a vulnerable point of the conventional 6T SRAM cell, it results in the alteration of the stored data within the cell, leading to a SEU. This work proposes two novel SRAM cell designs to address this problem. The first proposed design has the capability to recover from SEUs occurring at all of its sensitive nodes. It exhibits better write performance due to the use of power cut-off transistor with VGND and ST action. It also has better read performance in terms of read delay and read stability, due to the lower BL capacitance. Furthermore, the proposed design one consumes less power due to the use of stacking effect and single BL structure. The second design is capable of withstanding and recovering from both SEU and SEMNU. It demonstrates better write performance due to the presence of fewer transistors in its write path. Owing to the reduced BL capacitance, it also have better read performance. Additionally, the second design uses less power consumption, as a result of reduced BL capacitance and leakage components along with stacking effect.