DESIGN AND IMPLEMENTATION OF LOW POWER ARITHMETIC AND SHIFT REGISTER CIRCUITS USING GDI TECHNIQUE

Abstract

This thesis presents a comparative study of GDI and TGDI techniques, implemented and analyzed on both combinational and sequential digital circuits, including D Flip-Flops, Ripple Carry Adders (RCA), Carry Select Adder (CSA), Serial-In Parallel-Out (SIPO) shift register, and Linear Feedback Shift Register (LFSR). The arithmetic circuits under consideration Ripple Carry Adder (RCA) and Carry Select Adder (CSA) were designed using both GDI and TGDI logic styles. Simulation results using Cadence Virtuoso at 2V and 180nm CMOS technology demonstrated that the TGDI based RCA achieved a 38.2% reduction in delay and a 21.8% improvement in power-delay product (PDP) compared to its GDI counterpart. Similarly, the TGDI based CSA showed a 38.4% reduction in delay and a 23.1% improvement in PDP over the GDI based design. These enhancements confirm the effectiveness of TGDI logic in improving circuit speed and energy efficiency, making it a promising choice for arithmetic operations in low-power digital systems. For shift register-based sequential circuits, including the Serial-In Parallel-Out (SIPO) shift register and the Linear Feedback Shift Register (LFSR), TGDI logic again outperformed its GDI counterpart. The TGDI based SIPO circuit showed a 41.6% delay reduction and a 25.8% improvement in PDP, while the LFSR design achieved a 33.8% lower delay and a 17.1% enhancement in PDP. Despite slightly higher power consumption, TGDI’s reduced delay leads to better overall energy efficiency and performance. These results confirm TGDI's strong potential in modern VLSI designs where compactness, speed, and power efficiency are critical.