NANO-SCALE, TEMPERATURE SENSITIVE, ANALYTICAL MODELING INCORPORATING QUANTUM EFFECTS OF SC, JL, DG STACK (SC-JL-DG) MOSFET FOR ANALOG INDUSTRY APPLICATIONS AT LEADING FREQUENCIES

Abstract

This work presents an in-depth investigation into the analog and radio- frequency (RF) performance characteristics of a novel Junction-Less Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL-DG-MOSFET) architecture featuring a gate oxide stack. The study specifically targets the influence of device scaling and structural modifications on analog performance metrics and their suitability for high-performance, low-power analog/RF circuit applications. A significant aspect of the device's operation is the emergence of quantum mechanical effects due to aggressive channel length scaling, which plays a vital role in determining its small-signal behavior. Key Figures of Merit (FOMs) for analog design are analyzed to evaluate the efficiency and robustness of the JL-DG-MOSFET. These include the cut-off frequency (fT), gain-frequency product (GFP), transconductance-frequency product (TFP), output conductance (gd), Early voltage (VEA), intrinsic gain (AV), transconductance efficiency (gm/ID), and the transconductance (gm) itself. The behavior of these parameters is critically assessed to determine the device's amplification capabilities, signal bandwidth handling, and overall analog reliability. All simulations and characterizations are conducted using the ATLAS device simulator, which allows for precise numerical modeling of the JL-DG- MOSFET under varying biasing and geometrical conditions. The simulated results consistently align with theoretical expectations, validating the physical modeling and demonstrating the potential of this device structure for future analog and RF integrated circuits. The results not only confirm the benefits of using a junction-less structure in reducing leakage and variability but also highlight the advantages of double-gate control in enhancing electrostatic integrity and analog responsiveness. This research provides a valuable framework for understanding the analog design trade-offs in emerging multi-gate, junction-less transistors and contributes to the broader effort of developing energy-efficient, scalable analog devices for next- generation nanoscale CMOS technologies.