DIGITAL MOS LSI CIRCUITS DESIGN OF 4X4 6T SRAM ARRAY

Abstract

Progress in CMOS and bigger need for quick, powerful digital systems, building effective memory subsystems is now very important. Since it is both fast and stable, Static Random-Access Memory (SRAM) is still important, especially for on-chip cache systems. In this work, the schematic design and simulation of a 4×4 SRAM array are presented, all using 6-transistor (6T) cells and 130nm CMOS technology.Important elements found in the architecture include a 2×4 row decoder, precharge circuitry on the bit lines and write drivers. Initially, the design process happened and was approved with the SYMICA EDA environment at the beginning or schematic level. These parameters were evaluated by extracting read delay, write delay and Static Noise Margin (SNM) during simulation.According to the simulation, the time for reading is 0.123 ns and the time for writing is 0.254 ns. Changes in conditions do not greatly affect the SNM read, hold or write margins, with numbers of 0.34 V, 0.13 V and 0.53 V, respectively, confirming the stability and noise resistance of the storage. The study also considers the effects of changing transistor sizes and circuit arrangements on how stable, quickly operating and space-efficient SRAM is, showing you the compromises needed for best results.This work serves as a foundational study for scalable SRAM architectures and demon-strates a complete design flow suitable for integration in low-power, high-performance digital systems. In addition, this research is in line with the SDGs set by the United Nations. Advantages obtained through semiconductor memory and innovative digital circuit design help achieve SDG 9 (Industry, Innovation and Infrastructure) directly. In addition, designing VLSI systems that consume less energy and take up less space supports SDG 12 (Responsible Consumption and Production) which leads to sustainable and environmentally friendly technology.