DESIGN AND ANALYSIS OF LOW POWER COMBINATIONAL CIRCUIT USING REVERSIBLE GATE

Abstract

The increasing demand for low-power and high-performance digital sys- tems has made power consumption a primary design constraint in modern VLSI circuits. Traditional irreversible logic circuits dissipate significant energy due to information loss during computation, as described by Lan- dauer’s principle. Reversible logic offers a compelling solution by ensuring a bijective relationship between inputs and outputs, theoretically elimi- nating information loss and minimizing dynamic power dissipation. This thesis presents the design and implementation of reversible com- binational logic circuits using two custom-designed reversible gates—R-I and R-II. These gates are capable of realizing fundamental logic func- tions with minimal garbage outputs and constant inputs. The circuits are implemented at the transistor level using pass transistor logic (PTL), which offers reduced area and power consumption compared to conven- tional CMOS implementations. To further reduce power dissipation, particularly leakage and short- circuit power, power gating is integrated into the reversible designs. High- threshold sleep transistors are used to disconnect idle logic blocks from the power supply, thereby achieving significant energy savings. The designs are simulated using Cadence Virtuoso on a 180nm CMOS technology node. Transient analysis is performed to evaluate power metrics and propagation delay. Simulation results show that the integration of power gating in re- versible circuits leads to a reduction of up to 40% in total power consump- tion, with only a marginal increase in propagation delay. The proposed R-I and R-II based designs also outperform equivalent standard CMOS circuits in terms of power efficiency. These findings validate the proposed methodology as a promising approach for low-power digital circuit design in future VLSI systems.