ACHIEVING GLITCH FREE CROSS DOMAIN CROSSING SIGNAL

Abstract

Glitches—unintended signal transitions—pose significant challenges to the performance and reliability of digital circuits, particularly in synchronous systems and complex System-on-Chip (SoC) designs with multiple clock domains. This paper focuses on employing structural verification techniques to achieve glitch-free circuit operation. We investigate and mitigate glitch occurrences early in the design process through the application of advanced verification methodologies, including formal verification and simulation-based approaches. The study begins with a comprehensive analysis of the origins and types of glitches in digital circuits. Subsequently, we introduce structural verification frameworks specifically designed to identify and rectify potential glitch- inducing configurations. Furthermore, in the context of increasingly intricate SoC designs incorporating multiple clock domains, we present a solution for detecting clock domain crossing (CDC) glitches by integrating formal verification and static timing analysis techniques. This paper also explores the utilization of formal verification tools for sequential equivalence checking between a flawed design and its corrected version when CDC glitches are discovered at later stages of the design cycle. We model, simulate, and verify designs against predefined glitch-free specifications using industry-standard tools to demonstrate the effectiveness of the proposed techniques.