IN MEMORY COMPUTATION BASED BOOLEAN AND LOGIC CIRCUIT DESIGN

Abstract

Data organisation is a very important task today. As we already know data stores digitally so there comes issue of accessing time. Today electronics system and gadgets are increasing very fast so data also increasing. Because of more data there becomes accessing of data rate slow. Today we are working with AI, machine learning, live project, live location, satellites, antenna, radio system many things are totally based on data speed. We cannot compromise with latency for a critical work. This is possible that we can make our memory system fast as well implementation of some basic operation inside memory only. In-Memory Computing is a technique, in which we store our data in RAM rather than slow server or disk. As our all system based on Von Neumann architecture and this architecture having both power and memory wall. This cases a bottleneck on performance of system. In memory computing is a good way to break this bottleneck and make our system to free from memory and power wall. This project intends to implementing Boolean and logic circuit design using In-Memory computing technique. This project is combination of two things, first one to select a proper SRAM (Static Random-Access Memory) and second is, with help of in-memory computing scheme implementation of Boolean and logic circuit. In this work we are presented what is SRAM and what is issue with 6T SRAM, 8T SRAM and 9T SRAM. Here also presented in-memory computation technology. The Boolean logic operation are demonstrated with 9T SRAM cell in 250 nm, 90nm and 22nm CMOS technology with help of Tanner and Cadence tool. The NAND, AND, NOR, OR, EXOR, EXNOR Boolean logics as well some combinational circuits are demonstrate using 9T SRAM cells with the proposed sensing scheme to verifying the In-Memory computations ability of 9T SRAM.