ANALYSIS AND IMPLEMENTATION OF DCT & DHT RECURSIVE STRUCTURES IN VERILOG

Abstract

The paper presents the implementation and analysis of a recursive Discrete Cosine Transform (DCT) and Discrete Hartley Transform (DHT) using Verilog. Knowing that there has been a growing demand for high speed and resource efficient systems there is a need for implementations that are both fast and lightweight, so the proposed work aims to design a hardware optimized version of the DCT and DHT using the recursive algorithm with an IIR filter based structure to improve performance and reduce complexity. DCT computations are mainly used in applications like signal processing and image compression, thus the proposed design aims to enhance the speed and resource efficiency of DCT computations. Earlier implementations on Verilog have been done for 𝑁 = 8, the proposed research work moves forward with the implementation of 𝑁 = 2௥, thus the verilog module are designed in a generalized manner. While, in the implementation and analysis of a recursive Discrete Hartley Transform (DHT) algorithm for input sequences of length N, where N = 2m and m >=2 is done Verilog. The simulation and synthesis results from MATLAB Simulink validate the correctness of the modules and functions applied and the performance of the design. The advantages of the proposed recursive structure architecture are that it reduces the number of adders and multipliers required for DCT and DHT computations. In traditional methods, the number of operations is dependent on the value of the input sequence length N. Whereas, the proposed recursive structure helps to maintain a fixed number of multipliers and adders regardless of N. This makes the structure more efficient, and this is achieved by reusing intermediate results and processing data in smaller manageable groups. This also helps in reducing the truncation errors, leading to higher accuracy in computations. This methodology is implemented using Verilog to demonstrate how much feasible the recursive architecture is. This makes it suitable for real-time applications on physical hardware structures. This research contributes to the ongoing efforts to optimize the DCT and DHT computations and thus it paves the way for more efficient compression and processing technologies. The proposed architecture suits real-time signal processing systems such as radar communication v and imaging. The proposed methodology is applied in Verilog to check its feasibility. The results show that the structure is efficient in computing the DCT and DHT coefficient with minimum input-output ports, hardware complexity, and power consumption which are highly useful in parallel VLSI implementations.