DESIGN AND IMPLEMENTATION OF LOW POWER AND HIGH-SPEED VOLTAGE LEVEL SHIFTER

Abstract

Voltage Level Shifters (VLS) are critical blocks in modern integrated circuits, especially in systems-on-chip (SoCs) where several voltage domains exist, for the best power efficiency and performance. With scaling technology and the trend toward lower supply voltages, the need for efficient, reliable, and high-speed voltage level shifters has been enormous. Voltage level shifter circuits enable signal communication between voltage level differing blocks without compromising signal integrity or adding excessive power loss. This thesis starts with an extensive overview of the current voltage level shifter architectures, ranging from the conventional voltage level shifter to the wilson current mirror voltage level shifter and other prominent topologies. Such architectures are thoroughly evaluated. The designs of the voltage level shifters proposed in this thesis are optimized to cater to various use cases, from energy-limited devices like battery-wearables to high-speed systems. The simulation results indicate that the power dissipation and delay of propagation of the designed circuits are minimal, striking a reasonable balance between speed and power efficiency in a practical sense. The results highlight the flexibility of the design to modern mixed-voltage systems and offer valuable insights into effective voltage level shifter circuit design.