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DC Field | Value | Language |
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dc.contributor.author | KUMAR, ANIKESH | - |
dc.date.accessioned | 2025-07-08T08:41:11Z | - |
dc.date.available | 2025-07-08T08:41:11Z | - |
dc.date.issued | 2025-05 | - |
dc.identifier.uri | http://dspace.dtu.ac.in:8080/jspui/handle/repository/21793 | - |
dc.description.abstract | The rapid proliferation of the Internet of Things (IoT) has revolutionized the digital ecosystem by interconnecting billions of devices across diverse domains such as healthcare, industrial automation, smart homes, and environmental monitoring. Despite its transformative impact, the IoT paradigm brings forth critical security challenges, particularly due to the stringent constraints of power, memory, and processing capabilities inherent in embedded devices. Conventional cryptographic algorithms like the Advanced Encryption Standard (AES), while offering robust security, are computationally intensive and thus ill-suited for such resource-constrained environments. In response to this challenge, the present thesis introduces a novel, lightweight Substitution-box (S-Box) architecture designed specifically for secure cryptographic operations within IoT ecosystems. The proposed design synergistically integrates the chaotic behavior of the logistic map with session-specific keying strategies to construct highly nonlinear, dynamic, and key-dependent S-Boxes. This hybrid approach ensures a high level of security while maintaining minimal computational overhead, making it particularly suitable for embedded implementations. The S-Box was implemented and evaluated on the STM32F401RE microcontroller—an ARM Cortex-M4 based platform that typifies the limitations and capabilities of modern IoT hardware. Cryptographic performance metrics indicate a nonlinearity score of 107, a differential uniformity of 4, and strong adherence to the Strict Avalanche Criterion (SAC) and Bit Independence Criterion (BIC), all of which are desirable properties for thwarting linear and differential cryptanalysis attacks. Furthermore, the statistical quality of the S-Box outputs was validated using the NIST SP800-22 suite, affirming its randomness and resistance to statistical attacks. From a hardware efficiency standpoint, the design demonstrates impressive performance with a measured power consumption of merely 0.45 milliwatts and an average execution latency of 6.3 microseconds per substitution operation. These results substantiate the S-Box’s capacity to operate effectively in ultra-low-power environments without compromising on cryptographic strength. Overall, this work contributes a secure, efficient, and scalable cryptographic primitive tailored to the nuanced demands of modern IoT applications. The fusion of chaos theory and dynamic keying mechanisms presents a promising avenue for future research in lightweight cryptographic solutions optimized for embedded and edge computing platforms. | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartofseries | TD-8004; | - |
dc.subject | S-BOX DESIGNS | en_US |
dc.subject | IOT APPLICATIONS | en_US |
dc.subject | STRICT AVALANCHE CRITERION (SAC) | en_US |
dc.subject | RAPID PROLIFERATION | en_US |
dc.title | LIGHTWEIGHT S-BOX DESIGNS FOR SECURE IOT APPLICATIONS | en_US |
dc.type | Thesis | en_US |
Appears in Collections: | M.E./M.Tech. Information Technology |
Files in This Item:
File | Description | Size | Format | |
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ANIKESH KUMAR M.Tech.pdf | 878.8 kB | Adobe PDF | View/Open |
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