ANALOG UNIVERSAL FILTER DESIGN USING CMOS VDCC AS AN ACTIVE BUILDING BLOCK

Abstract

This study validates design and implementation of voltage-mode (VM) triple-input, single-output (TISO) biquad filter that employs a single voltage differencing current conveyor (VDCC) as the core active building block. The research encompasses a comprehensive study of various analog filter responses, including low-pass, high-pass, band-pass, band stop and all-pass filters, emphasizing the VDCC's versatility and superior performance metrics. The study is structured to include a detailed theoretical analysis and extensive PSPICE simulation of CMOS based VDCC filters. The theoretical analysis entails deriving the design equations and comprehending the operational principles of VDCCs in filter circuits. These models are subjected to rigorous validation through extensive simulations using advanced electronic design automation (EDA) tool like PSPICE. Additionally, the circuit allows for the adjustment of the cutoff frequency (ω₀) and pole quality factor (Q). The configuration was designed and simulated using PSPICE, and the simulation results were cross-verified with theoretical expectations. In conclusion, this research makes a significant contribution to the domain of analog filter design by presenting VDCC as a robust and efficient alternative to conventional methodologies. The findings substantiate the practical advantages of VDCC, paving the way for future innovations in analog signal processing. This work establishes a solid foundation for further exploration and application of VDCC in various analog circuit designs, promising enhanced performance, reduced power consumption, and increased versatility in modern electronic systems.