SELF-CONSISTENT LCAO-BASED DFT ANALYSIS OF FERROELECTRIC AND GATE MATERIAL ENGINEERED NEGATIVE CAPACITANCE FET FOR IMPROVED DEVICE-CIRCUIT PERFORMANCE

Abstract

This thesis explores the challenges associated with Negative Capacitance Field-Effect Transistors (NCFETs), an emerging technology that promises to overcome traditional CMOS devices' fundamental power efficiency limitations. NCFETs, by utilizing a negative capacitance effect in ferroelectric materials, offer a solution for lowering subthreshold swing (SS) beyond the thermionic limit, thus reducing power consumption in next generation transistors. This research systematically investigates these problems through simulation-based approaches. A detailed analysis of ferroelectric materials used in NCFETs, such as Hafnium-based oxides, is presented to identify performance degradation factors. The study also proposes optimized device architectures and material compositions to mitigate these effects. The findings contribute to understanding NCFET limitations and offer pathways for overcoming these barriers, providing insights for further research in low-power semiconductor technologies. At this beginning, the effect of ferroelectric material on the substrate region is considered. The ferroelectric material is placed between the high-k HfO2 layers in the conventional MOSFET’s substrate, and this modified structure is termed FE-MOSFET. A study of the analog and RF parameters was investigated. The VISUAL TCAD simulator does all the simulation work. Then, the Quantum ATK simulator examines the reliability of silicon doped HfO2 as a ferroelectric material with different concentrations of silicon. The DFT analysis comparison of hafnia and 1Si-HfO2 and 2Si-HfO2 is done. DFT analysis contains the band structure and PDOS data corresponding to different materials. The effect of this 2Si-HfO2 as a ferroelectric material is taken into account on the performance parameters of MOSFET, and the modified device with 2Si-HfO2 as a ferroelectric in gate stack and high k HfO2 in substrate region is termed as Modified NCFET. Further, to ensure the device’s Rashi Mann viii reliability, it is crucial to explore its characteristics, and the temperature variations taken into account. The performance parameter comparison of Modified NCFET is done with the conventional NCFET structure. Moreover, the impact of the high-k spacers on the analog/RF and inverter-based parameter performance of Gate-Stacked NCFET (Modified NCFET) is examined. Spacer materials are HfO2, SiO2, and helium (due to the unavailability of air molecule structure in the quantum ATK database, we investigate the structural properties of helium (k=1.000074 at 00 C and 1atm), which has nearly the same dielectric constant of air (k=1).) Self-consistent LCAO-based DFT analysis is done for the spacer materials regarding band structure, PDOS, and Hartree potential. Four configurations are simulated for this analysis, defined as GS-NCFET with no spacer (S0), GS-NCFET with AIR spacer (S1), GS-NCFET with SiO2 spacer (S2), GS-NCFET with HfO2 spacer (S3). After analyzing the electrical properties of the proposed device (GS NCFET), the device modelling is done using the VISUALFAB simulator. The Cadence Virtuoso tool creates two symbols corresponding to N-GS-NCFET and P-GS-NCFET. Then, the digital application of GS-NCFET is shown as NAND, NOR, and NOT logic gates. It was found that the digital applications of GS-NCFET in terms of logic gates show the device is working properly with expected input-output curves. Thus, GS-NCFET can be considered a promising candidate for use in low-power, analog, RF, and high-performance CMOS circuits due to its high switching ratio, lower leakage current, better reliability in terms of temperature, and superior static, analog, and RF performance, suppressed SCEs and parasitic capacitances.