DEVELOPMENT OF CM CIRCUITS FOR ANALOG SIGNAL PROCESSING AND SIGNAL GENERATION

Abstract

Over the past couple of decades, analog signal processing (ASP) has seen a paradigm shift from voltage mode (VM) to current mode (CM) design technique due to inherent merits of the CM processing. Though the design techniques are fundamentally limited by device characteristics; however, for specific applications CM design may provide one or more of the following advantages: higher bandwidth and slew rates, lower power consumption and better signal linearity and accuracy. Additionally, current mode circuits may lead to significant chip area saving also owing to their less complex designs than the voltage mode circuits. The merits of CM design has led researchers to explore variety of CM analog building blocks (ABBs) and existence of numerous such blocks in literature is a testament of the same. These ABBs find applications in various analog signal processing and generating circuits. The voltage differencing transconductance amplifier (VDTA) is one among the other CM ABBs which is conceptually presented by Biolek et al. in 2008. The VDTA is a voltage input current output ABB having two transconductance gain stages which helps in realization of resistor-less compact CMOS applications. Additionally, the transconductances of the VDTA can be tuned through bias current which facilitates electronic tunability of the system parameters. Thus, VDTA is a preferred choice for designing on-chip high frequency applications. Its first CMOS realization was present by Yesil et al. in 2011. Further, fractional order (FO) circuits and systems are gaining researcher’s increased attention as these provide extra degree of freedom and models natural systems more precisely as compared to their integer order counterparts. Fractional order elements (FOEs) namely fractional capacitors and inductors (FCs and FIs) are the basic building blocks for realizing FO circuits. Though the FCs and FIs are not commercially available as circuit components but a variety of rational approximation methods exists in the open literature to emulate the FCs. The FIs can be derived through classical methods which are used in integer domain for emulating inductors using capacitors. Thus, combining the advantages of CM processing with fractional order designs researchers have proposed a wide range of signal processing and generation vi application using variety of ABBs. This research trend has been explored in context of VDTA having identified the advantages of VDTA based designs in the presented work. Additionally, this work also presents few integer order applications of the VDTA. Exploring significant avenue of the active inductance emulation, VDTA based compact, resistor-less generic inductance emulator (IE) have been proposed. This emulator can be configured as (i) integer order positive inductance emulator (ii) integer order negative inductance emulator (iii) fractional order positive inductance emulator and (iv) fractional order negative inductance emulator. Research contribution in the domain of analog filter design is presented in the form of a classical integer order filter and two α-order voltage mode fractional order filters (FOFs) based on VDTA. The integer order filter is a multiple input multiple output biquad filter. Moving on to the fractional order counterparts, first FOF represents voltage mode multiple input single output universal configuration whereas, second FOF topology presents voltage mode single input multiple output multifunction structure. Further, there is considerable scope for exploring improved design of higher order sinusoidal oscillators. In that attempt, a third order sinusoidal oscillator (TOSO) has been proposed using a single VDTA. In this work proposition of new CMOS structures of the VDTA are also explored and its outcome has led to the proposition of two new transconductance boosted architectures of the VDTA. The former structure is based on the partial positive feedback whereas the later utilizes the concept of gate to source voltage variation for transconductance enhancement. The proposed designs are verified either through simulations or combination of simulations and experimental validation. The simulations are carried out either with Cadence tool suite or PSPICE using 180 nm CMOS technology parameters. For experimental purpose, the VDTA is implemented using off the shelf IC LM13700 with ±10V supply voltage.