ANALYSIS AND DESIGN OF CMOS MULTISTAGE AMPLIFIERS

Abstract

A multistage amplifier is an essential component of analog signal processing. Although it provides high gain but the complexity of the amplifier increases with the number of stages. Moreover, a multistage amplifier produces a large number of comparable poles and zeros, which causes the phase margin to deteriorate. As a result, the stability of the amplifier is reduced. Consequently, the frequency compensation techniques become crucial when designing multistage amplifiers in order to improve the stability of the amplifier. However, in addition to addressing the amplifier’s stability, the frequency compensation technique should enhance the gain bandwidth product (GBW), phase margin, and slew rate of the amplifier. The key objective of this thesis is to propose improved three stage amplifiers using different frequency compensation techniques. One of the conventional frequency compensation techniques called Reversed Nested Miller Compensation (RNMC) is widely used in three stage amplifiers. However, RNMC suffers with the problem of Right Half Plane (RHP) zero, which reduces the phase margin of the amplifier. In order to address the RHP zero problem of RNMC, the proposed amplifier 1 utilizes Flipped Voltage Follower (FVF) in the inner compensation loop of RNMC. Moreover, it improves the frequency response of the amplifier. Further, a feed forward path is employed to enhance the transient response of the amplifier. Another variant of voltage follower called Folded Flipped Voltage Follower (FFVF) is exploited in the inner compensation loop of RNMC in the proposed amplifiers 2-5. It resolves the RHP zero issue and improves the Gain Bandwidth Product (GBW) of the amplifiers. Moreover, the proposed amplifiers 3-5 also make use of a resistor in the outer compensation loop. It results in double pole-zero cancellation, which enhances the phase margin. vi Additionally, the proposed amplifiers 4 and 5 employ the self cascode structure and DTMOS transistors in the input stage, respectively. This results in better GBW of the amplifiers. The proposed amplifiers 2-5 also take advantage of the feed forward path to improve the transient response. Further, an active LHP zero circuit is employed in the proposed amplifiers 6-9 to cancel the parasitic pole of the second stage. It enhances the GBW of the amplifiers. Additionally, a Miller capacitor with resistor ensures the stability of the amplifiers. Moreover, a self cascode structure and self cascode with DTMOS are used in the input stage of the proposed amplifiers 6 and 7, respectively. It results in better GBW of the amplifiers. The GBW is further enhanced by employing a modified self cascode structure in the first stage of the proposed amplifiers 8 and 9. Moreover, a feed forward path is exploited to improve the transient response of the proposed amplifiers 6-9. To further enhance the frequency response of three stage amplifiers, a class AB FVF is utilized in the inner compensation loop of RNMC in the proposed amplifiers 10 and 11. Additionally, a slew rate enhancer circuit and a feed forward path are exploited to improve the transient response. In this thesis, the small signal analysis is performed for all proposed amplifiers to find out the transfer function, which helps in evaluating the GBW and the stability of the amplifiers. Further, the performance of all proposed amplifiers is compared with their counterparts. The functionality of the proposed amplifiers is verified using TSMC 0.18 µm CMOS technology parameters in Tanner tool. Corner analysis, supply voltage variation, and Monte Carlo analysis are carried out to confirm the robustness of the proposed amplifiers.