STUDIES ON TECHNOLOGY COMPUTER AIDED DESIGN OF DOUBLE METAL NEGATIVE CAPACITANCE FET USING DFT AND MACHINE LEARNING APPROACH FOR ANALOG/SENSING

Abstract

The exponential growth in transistor density has been the driving force behind advancements in computing power, energy efficiency, and cost reduction for decades. As transistor dimensions shrink, the gate loses control over the channel, causing issues such as threshold voltage roll-off, increased leakage currents, drain-induced barrier lowering (DIBL) etc, higher transistor densities increase power consumption per unit area. Shrinking device dimensions exacerbate parasitic capac itance, parasitic resistance, heat dissipation etc. The primary issue with conventional integrated circuits and systems based on CMOS technology is increasing power consumption. Due to the ability to reduce supply voltages using steep-subthreshold swing Field Effect Transistor devices, they have been proposed as a viable option for future circuits and systems that prioritize energy efficiency. The scientific and academic communities have shown significant interest in Negative Ca pacitance Field Effect Transistors (NCFETs). NCFETs offer numerous notable benefits compared to conventional FETs, primarily due to unique characteristics of the ferroelectric material used in their gate stack. The advantages of NCFETs include low power consumption, increased drive current, reduced subthreshold swing, and higher energy efficiency. The property of NCFETs that allows them to achieve low off-current (Iof f ) and comparable on-current (Ion) at low supply voltages means that they work effectively at low switching voltage and with less power consumption. Different types of NCFETs depending on their structural integra tion with ferroelectric materials and engineering such as Planar NCFET, NC FinFET, Nanowire NCFET, NC Tunnel FET, etc have been analysed in various literature, each configuration has viii Yash Pathak distinct benefits but also poses various obstacles in their functioning like ferroelectric material sta bility, control of ferroelectric properties, power-performance trade-offs, temperature sensitivity, and overall device reliability. To counter these challenges, a new device structure, DM NCFET (Double Metal NCFET) is proposed and examined in this thesis. It comprises two metallic layers below the ferroelectric material with stacked insulator in between, resulting in MFMIMIS (Gate Metal Ferroelectric-Metal-Insulator-Metal-Insulator-Semiconductor) configuration. The idea behind the inclusion of metal layers in the structure is due to its several benefits. The metal layer helps in redistributing the electric field across the ferroelectric and insulator layers. The metal layer also acts as a barrier, preventing direct tunnelling currents between the semiconductor and ferroelectric layers, thus enhances device reliability by minimizing leakage. The metal layer also provides bet ter control over the interface properties, which reduces hysteresis effects in the ferroelectric layer. The metal layer can act as a heat sink, dissipating heat generated during device operation, thus improves the thermal stability and longevity of the device. Further, by isolating the ferroelectric and insulator layers, the metal layer minimizes defects at their interface, thus enhances the overall performance and reliability of the device. Subsequently, spacer technology is also incorporated in the DM NCFET configuration to form DM-NCFET (spacer) to further improve device performance and scalability. Spacers are typically insulating materials, such as silicon nitride (Si3N4) or silicon dioxide (SiO2), formed on the sidewalls of the gate stack. They reduce hot-carrier injection (HCI), thereby improves device reliability and reduces electric field peaks at the drain junction. Spacers electrically isolate the gate electrode from the source/drain regions, thus prevent parasitic capac itance and any associated leakage paths. Spacers also help in achieving self-aligned source and drain regions during fabrication. So, by providing precise control over doping, isolation, and stress, spacers in general enhance the reliability and efficiency of the device. Thus, this proposed structure presents a promising direction for overcoming the limitations of conventional NCFETs, especially as technology nodes scale down. It provides a pathway to achieve a more promising device for meeting the demands of modern electronics. Initially, the analog and RF (Radio Frequency) performance of the ferroelectric Field Effect Transistor device, specifically the DM-NCFET with and without a spacer were studied. The pro posed DM-NCFET (spacer) improves the ON-current (Ion) by 25% as compared to the DM-NCFET without a spacer, reduces leakage current (Iof f ) by approximately 37%, enhances the switching ra ix Delhi Technological University, Delhi-42 Yash Pathak tio (Ion/Iof f ) by 99%, increases the threshold voltage (Vth) by 0.29%, and lowers drain-induced barrier lowering (DIBL) by 17.6%. We also examined various analog parameters to improve the performance of the DM-NCFET with a spacer at 300K, including transconductance generation fac tor (TGF), transconductance (gm), intrinsic gain (Av), early voltage (Vea), intrinsic delay (Ti), and some RF parameters like gain transconductance frequency product (GTFP), cut-off frequency (Ft), and gain frequency product (GFP). At 300K, the DM-NCFET(spacer) shows improved performance for these parameters compared to higher temperatures (400K and 500K). Simulated results using Visual TCAD confirm the high compatibility and enhanced performance of DM-NCFET(spacer) at room temperature (300K). Additionally, the gate electrode work function was varied using ma terials like Palladium, Chromium, and Tungsten. Palladium with a work function of 5.3eV, showed the best performance with improvement in leakage current by 106 times and switching ratio by 107 times compared to Chromium. Furthermore, the DM-NCFET is explored for biosensing applications, analyzing the effects of nano cavity gaps with biomolecules like proteins, cholesterol oxidase (ChOx), streptavidin, and uricase. Electrical characteristics such as threshold voltage and switching ratio (Ion/Iof f ) are higher with biomolecules compared to without biomolecules. Protein sensitivity is improved by 1.11 times, and the detection limit is higher by 1.012 times. The biosensor’s sensitivity is increased with increase in dielectric parameter of the biomolecules, and modulation of the cavity gap length (from 8nm to 12nm). Visual TCAD software was used for all the simulations, showing that the DM-NCFET biosensors are highly sensitive with low-power consumption, thus suitable in numerous applications like checking infections, food investigation, crime detection, ecological monitoring, and biomedical field. Moreover, the analog/RF and linearity parameters of Single Metal Double Gate NCFET (SM DGNCFET) and Double Metal Double Gate NCFET (DM-DGNCFET) are observed using Cogenda Visual TCAD and Quantum ATK tool. SM-DGNCFET demonstrated better performance with a 279 times higher switching ratio, 54% lower DIBL, reduced SS, and improved transconductance, TGF, and RF parameters like TFP, confirming the enhanced device’s reliability and stability. Linearity parameters such as second and third-order transconductance (gm2, gm3) and voltage intercept points for 2nd and 3rd order are also improved. The Tran-Blaha modified Becke-Johnson (TB-mBJ) approximation provided accurate band gap calculations, and DFT-based atomic studies x Delhi Technological University, Delhi-42 Yash Pathak with 12.5% Si doping in HfO2 crystals showed better conductivity for the device. Further, the machine learning approach for predicting key analog and RF parameters of NCFETs is also explored using Visual TCAD and Python. The algorithm of an artificial neural network effectively predicted multi-input to single-output relationships, reducing computational costs. Sim ulations demonstrated that DM-DGNCFETs performed optimally at T=300K, Tox=0.8nm, and Tsub=3nm, improving the switching ratio and reducing leakage current. Notably, at T = 300K, the switching ratio is higher and the leakage current is 84 times lower compared to T = 500K. Sim ilarly, at ferroelectric thicknesses TF e = 4nm, the switching ratio improves by 5.4 times compared to TF e = 8nm. Furthermore, at substrate thicknesses Tsub = 3nm, switching ratio increases by 81% from Tsub = 7nm. For oxide thicknesses at Tox = 0.8nm, the switching ratio increases by 41% compared to Tox = 0.4nm. The analysis reveals that TF e = 4nm, T = 300K, Tox = 0.8nm, and Tsub = 3nm represent the optimal settings for DM DGNCFET, resulting in significantly improved performance. Additionally, experimental circuit designs of Ion-Sensitive FETs (ISFETs) for pH sensing are investigated. The gate electrode work function on ISFETs was rigorously studied using Cogenda Visual TCAD, with molybdenum showing better results than aluminum. Based on its I-V charac teristics, it may deduce that molybdenum, with a work function of 4.75eV, has a larger threshold voltage, switching ratio (104 ) and lower leakage current (10−3 ) than aluminium at 300K. Compar ative studies of ISFET sensing layers (Al2O3, Si3N4, SiO2) indicated that Al2O3 displayed the best results for switching ratio, leakage current, sensitivity, and transconductance. The enhancement in pH sensing is also demonstrated experimentally with proper circuit designing of ISFET. ISFET display instability, often referred to as drift, in the form of a gradual, monotonic, temporal increase in the device’s threshold voltage. The validation of the observations is done by increasing the value of the pH as follows: 4.67, 5.9, 7.5, 8.57, and 9.3, which were checked by pH meter. In conclusion, DM-NCFET shows great potential for low-power, analog, RF, and sensing ap plications along with its compatibility with DFT and machine learning approaches as discussed comprehensively in this research work.