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DC Field | Value | Language |
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dc.contributor.author | KUMARI, NEELAM | - |
dc.date.accessioned | 2024-12-13T05:01:12Z | - |
dc.date.available | 2024-12-13T05:01:12Z | - |
dc.date.issued | 2020-05 | - |
dc.identifier.uri | http://dspace.dtu.ac.in:8080/jspui/handle/repository/21216 | - |
dc.description.abstract | Semiconductor product design”is a central processing unit (CPU) core”based SoC in which additional functionality”is provided by intellectual property (IP) cores connected to the CPU core. In every new generation of the SoC, more functionalities are added. In other words, it has a higher number of IPs compared to the previous one, increasing its complexity. The time required to confirm that the product behavior is in accordance with the specifications and/or datasheets also increases with complexity. So post and pre silicon validation with less consumption of time is required. Here the study of methods of pre and post silicon validation methods with some examples of IPs are taken. They are studied and their results are also studied. | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartofseries | TD-7555; | - |
dc.subject | PRE AND POST SILICON VALIDATION | en_US |
dc.subject | CPU | en_US |
dc.subject | SOC | en_US |
dc.title | PRE AND POST SILICON VALIDATION OF SOC | en_US |
dc.type | Thesis | en_US |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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NEELAM m.tECH.pdf | 775.48 kB | Adobe PDF | View/Open |
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