STUDY OF ALTERNATIVE LOGIC STYLES SUITABLE FOR LOW POWER VLSI DESIGN

Abstract

In the past decade, technological advancements in Very Large Scale Integration (VLSI) have increased integration density, pushing power to its limits and challenging packaging and cooling systems. The increasing demand for portable devices, notably smartphones, and the expanding adoption of Internet of Things (IoT) necessitate faster, power-efficient devices with extended battery life. As a result, it's crucial to develop energy efficient designs that offer improved performance. Static CMOS and dynamic domino designs have long dominated the digital arena, yet they have inherent limitations. Static CMOS faces challenges like increased input capacitance, limiting its energy efficiency as fan-in values rise. Dynamic domino design offers lower delay but at the cost of higher energy and sensitivity to process variations. Therefore, balancing power and speed in CMOS gate remain challenging due to energy-delay trade-off. To overcome these challenges, there is a growing need to search for logic styles and transistor technologies that can act as an alternative to existing CMOS based designs. Additionally, implementing power reduction techniques becomes imperative for these alternative logic styles to have less power. One such alternative logic style is Dual Mode Logic (DML) which offers dual mode functionality, i.e. static mode and dynamic mode, with low power and high speed. However, limited study has been conducted to reduce leakage power in the context of DML circuits. Therefore, leakage reduction techniques i.e. LECTOR and GALEOR are incorporated in footed DML design. Three designs are proposed, namely LECTOR with Dual Mode Logic (LDML), GALEOR with Dual Mode Logic (GDML) and v GALEOR with Dual Mode Logic with footed Diode (GDMLD), to reduce leakage in footed DML design. These designs use the concept of stacking to achieve leakage power reduction. Other than this, Dual Mode Transmission Gate Diffusion Input (DMTGDI) and Differential Cascode Voltage Switch Logic (DCVSL) are alternative logic styles that can also be explored for Power Delay Product (PDP) reduction. Two such designs- Modified Dual Mode TGDI (M-DMTGDI) and Dual Mode DCVSL (DM-DCVSL) are introduced in this work which offers dual mode functionality along with PDP reduction. In addition to this, the proposed M-DMTGDI design also overcomes the contention issue present in the existing DMTGDI design. Further the improved transistor technology, primarily Carbon Nanotube Field-Effect Transistor (CNTFET) , can be explored to implement designs, which already exist in MOSFET domain, so as to leverage the benefits of CNTFETs for their implementation. Such designs are put forward in this work, namely, CNTFET based footed DML (C-DML), CNTFET based DMTGDI (C-DMTGDI) and CNTFET based M-DMTGDI (C-MDMTGDI). These designs demonstrate superior performance over their CMOS counterparts, particularly in terms of reducing the PDP. Another area of research that has emerged in CNTFET domain is leakage power. Limited study has been conducted on the implementation of leakage reduction techniques in CNTFETs, using the methods previously developed for MOSFETs. So, for leakage reduction, three leakage reduction techniques namely LECTOR, GALEOR, and LCNT are also proposed for C-MDMTGDI design. Each of these proposed techniques significantly reduces leakage power but at the cost of delay. In this thesis, the performance of all the proposed designs is analysed and compared with existing counterparts in terms of power, delay and PDP. Functional verification is done vi for all proposed designs. The MOSFET based designs are simulated using Symica DE tool and HSPICE tool is used for simulating CNTFET based designs.