ANALYTICAL MODELING, SIMULATION AND CHARACTERIZATION OF JUNCTIONLESS ACCUMULATION MODE MOSFET FOR ANALOG AND RF CIRCUIT APPLICATIONS

Abstract

The persistent demand of the market for area- efficient and low power dissipating devices leads to continuous reduction in device size. It persuades the device engineers to develop such Integrated Circuits (ICs) with less fabrication complexity. Integrated circuit industry has revolutionized over the past few decades. Scaling has lead towards the compactness of these physical devices. The density of the transistors present over the chip doubles itself after every 18 months. This factor of scaling has given rise to many novel structures and devices. But as this dimension enters into nanometer regime, it brings about many difficulties known as Short- Channel Effects (SCEs) and Hot Carrier Effects (HCEs). SCEs include Drain Induced Barrier Lowering (DIBL) effect, threshold voltage roll- off, velocity saturation effect, etc. These effects can alter the device characteristics severely and needs to be minimized. Therefore, to overcome these complications, several novel device architectures involving device engineering techniques have been proposed to maintain the functioning and capabilities of the device inspite of scaling. Multiple gate transistors are becoming prevalent these days because of their scaling capabilities, complete depletion of the channel and more control of the gate over the channel region. These structures also help in reduction of the leakage currents and the SCEs to a greater extent. Nowadays, a new structure called Cylindrical Surrounding Gate (CSG) MOSFET has emerged, in which the gate wraps all around the silicon pillar. Thus, provides superior gate controllability, finer scalability, excellent compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) technology, much reduced SCEs, low leakage current and steep Subthreshold Slope (SS). These characteristics make CSG MOSFET as the ultimate short channel device for the future device technology. However, when the device dimensions are extremely scaled (below 22nm technology), higher source/drain resistance is formed due to the formation of abrupt source/drain p-n junctions. This in turn increases the fabrication complexity of the device and therefore, from the fabrication point of view, it is difficult to have control over these metallurgical p-n junctions. Hence, to endure with the future Ultra Large Scale Integration (ULSI) design, progressive changes in the elementary device design needs to be incorporated. A novel device structure called as Junctionless Transistor ix (JLT) was then proposed to overcome this problem of the increased source/drain resistance. JLT is uniformly heavily doped throughout the source, channel and drain regions either with n+ - n + - n + or p+ - p + - p + . Hence, there is no formation of p-n junctions between the source/drain and the channel regions. Due to elimination of junctions, JLT is easy to fabricate and also offers improved electrical properties. But because of the high doped channel, the mobility of the carriers gets degraded in the JLT. This problem of Carrier Mobility Degradation (CMD) leads to lower drain current and lower transconductance. So, another structure, junctionless accumulation-mode (JAM) MOSFET was introduced. In JAM MOSFET, the channel region’s doping is done slightly less than that of source and drain. The carriers get accumulated at the source channel-drain boundaries similar to an ohmic contact. On account of the higher doping present in the source and drain regions, it avoids high parasitic resistance. Also, due to lower doping present in channel region, it also overcomes the problem of CMD. Thus, provides more conductivity and better characteristics than JLT. JAM has reduced SCEs but they are still not negligible, so in this research work, techniques of gate metal engineering and gate stack engineering are therefore incorporated in JAM MOSFET and a new structure was proposed named Dual-Metal Gate Stack Engineered JAM-CSG (DMGSE-JAM-CSG) MOSFET. In a MOS device, a high electric field at the drain side causes impact ionization and tunnelling of the carriers, which are responsible for hot- carrier effect. In order to address this problem, high-k gate stack have been implemented in our proposed device architecture. Thus, use of gate stack helps eliminate the problem of leakage currents. Also, the implementation of dual metal gates of different work- functions enhances the gate transport efficiency resulting in excellent gate control, which further leads to high drain current and high transconductance. Hence, our proposed device, DMGSE-JAM-CSG MOSFET possesses better electrical characteristics as compared to the JAM-CSG MOSFET. This has been verified by both using both the analytical and simulation method. 2-D analytical modeling of DMGSE-JAM-CSG MOSFET has also been proposed to address center potential, electric field, subthreshold current, transconductance and various SCEs. Furthermore, the analysis is also done using different high- k gate stack materials. The exactness of this developed model is then established by comparing with the simulated outcomes. x The change in temperature varies the performance of the MOSFET, therefore, it becomes important to examine the impact of temperature upon the various characteristic aspects of the MOSFET. Therefore, to study the influence of temperature on our structure i.e., DMDG-JAM-CSG MOSFET, we have developed this structure’s temperature- dependent physics- based analytical model using the applicable boundary conditions. The characterization of the device is also studied at cryogenic temperatures. In addition to this, we have also performed the linearity assessment of our device by determining various figure of merits. Our research also proposes analytical modeling for Junctionless Accumulation-Mode Cylindrical Surrounding Gate (JAM- CSG) MOSFET-based biosensor used for label free electrical detection of the biomolecules (enzymes, cells, DNA, etc.). In this work, non-uniform doping in the channel of DMGAA-JAM-NWFET is also considered and improved characteristics over the uniformly doped channel were observed. Also, the influence of the straggle length parameter and peak doping concentration upon the device behaviour was also examined. All the device designs discussed above are elaborated in the dissertation. Also, the contribution of the research to the field of Nano Electronics is also discussed herewith.