LOW POWER, DUAL MODE OPERATIONAL 7T SRAM BIT CELL AND SENSE AMPLIFIER FOR PERFORMANCE ENHANCEMENT

Abstract

Cache memory is a key component for most microprocessors in embedded system. The increasing processing load has resulted in an upsurge in the demand for low power, high performance SRAM bit cells. The memory is formed by an array of bit cells for data storage, and its peripheral circuits. The peripheral circuit comprises of SA, row-column decoders, write drivers, and pre-charge circuitry. The 6T bit cell was the industry standard, but with decreasing technology node and VDD scaling the performance for the 6T cell is deteriorating. This has motivated researchers to design other bit cells. Altering the bit cell design mandates re-designing the sense amplifier topology as well to make it compatible with the modified cell design. In keeping with the same, four designs (7TP1, 7TP2, 7TP3, and 7TP4) of single ended, single port 7T bit cells are proposed. The cells differ from each other in terms of the number of multi-threshold devices and the read port topology adopted by the cell. The performance of the proposed of the four proposed cells is compared to identify the best design topology. Based on the comparison the 7TP3 cell is identified as the best topology amongst the four designs. Its HSNM and RSNM are high at 90 mV; the WM value is slightly high. While, the write time is considerably low at 10 ns. Additionally, its area is also towards the lower end in comparison to others and the design is also nearly square. Thus, 7TP3 cell design is accepted as the best design topology amongst the four proposed 7T bit cells. All the cells are designed at 32 nm technology node and simulated for 300 mV supply voltage. Thereafter, the performance of the proposed 7TP3 bit cell is compared against pre-exiting bit cells to validate its performance. The major highlights for the 7TP3 cell are - its read port which is designed to exclude the data node from read discharge current path and it use of a high performance transistor to improve write ability for the cell. Collectively, they help improve the read and write stability for the cell. The hold, read, and write noise margin for the cell are 90, 90, and 180 mV respectively for supply voltage of 300 mV. It requires a 10 ns pulse-width to perform a successful write operation. The robustness of 7TP3 cell is analyzed using its resilience to global variation analysis and temperature variation anlsyis. For the Monte Carlo analysis 6σ variation around the mean threshold value are taken for performance analysis, whereas for temperature variation v analysis the environment temperature for the simulation is varied from -10 ⁰C to 80 ⁰C. When subjected to global variations, the cell maintains read as well as hold SNM of 75 mV, while the WM is 215 mV. While for temperature variation analysis, the HSNM and RSNM are reduced by 0.1 mV/⁰C and the WM changes 0.2 mV/⁰C. This validates the performance of the proposed 7TP3 cell against both global and temperature variation analysis. This helps validate the reliability of the cell. The performance for the 7TP3 cell is compared against other 5T, 6T, 7T, 8T, 9T, 10T cells and is found to be superior. Its leakage current is low, while the ON current is high. Thereby, resulting in high current ratio value of 783 for the cell in comparison to its other pre-existing bit cells in comparison. The power consumption of the proposed bit cell is also found to minimal for all modes of operation. The standby power of the cell is calculated to be 8.4 and 1.05 pW for Q = ‘0’ and ‘1’, respectively. Moreover, the improvement in the performance is obtained for area as low as 0.539 µm2 . The area of 5T, 6T, 7T-1, 7T-2, 7T-4, 7T-5, 8T, 9T and 10T cell is greater than 7TP3 bit cell area by 22.17 %, 51.8 %, 35.8 %, 13.9 %, 30.4 %, 6.78%, 56.6 %, 63.3 % and 75.5 %. The design for the proposed single ended, single port 7T cells can operate only in this configuration. But, the growing popularity of hyper-personalized devices and round the clock connectivity has generated the need for a bit cell that can switch between low power and high speed operation. Thus, concept for a dual mode operational bit cell is proposed. The concept for the proposed dual mode operation cell describes a bit cell that has the capability to operate in two different design configurations. The selection of mode of configuration for the cell is dependent on the control signals for the cells. The control signals of the cell can steer into from one configuration into the other. To design the dual mode operational bit cell, one mode of operation is the single ended, single port mode of the 7TP3. To determine the second mode of operation for the cell, another 7T cell with single ended, dual port configuration is proposed. Thus, a single ended, dual port 7T cell is also proposed. The memory core and write port for the proposed dual port cell is similar the memory core and write port for the single ended, single port 7TP3 cell proposed in. The difference between the two topologies lie in their respective read port design. The read port and write port for 7TP3 are connected to a common bitline. Whereas, the read and write port for the dual port 7T cell are isolated and vi do not share a common bitline for operation. The cell is designed at 32 nm and its performance is compared against other pre-existing 7T bit cells. The cell is simulated for 800 mV as, various pre-existing bit cells performed reliability at this voltage. The stability analysis for the hold, read, and write operation for the proposed dual port 7T cell yields the noise margin for the three operations as 324, 324, and 488 mV, respectively. For a successful read and write operation pulse-width of 5 ps and 0.14 ns respectively are required. Temperature variation analysis yields 0.15, 0.15, and 0.24 mV/⁰C variation in hold, read, and write noise margin values, respectively. The leakage power consumption for the cell is 256 pW, while the read, and write power consumption for the cell are 6 µW and 1.9 µW, respectively. All the aforementioned merits for the proposed dual port 7T cell are achieved with a minimal layout area of 0.553 µm2 . Once the design for the single ended, single port 7T cell and the single ended, dual port 7T cell is finalized, the dual mode operational cell is designed. The dual mode operational cell is a versatile amalgamation of the aforementioned two cells with the capability to function in two different single ended configurations – single port and dual port. The bit cell is composed of eight transistors and is grouped into three sub-parts – single bit memory core, reading port and writing port. The single bit memory core of the reconfigurable memory is the part that stores the desired information. The read and the write port are the access circuitry that enable the device to read and write into the cell, respectively. The single port cell is more suitable for low power applications and the dual port cell is better for high speed operation. Therefore, as per the requirement of the circuit at a given instant, the different configurations for the cell may be used. All the proposed cells are of single ended nature owing to their better performance at lower supply voltage and high area density. This growing demand for single ended cells has also generated the need for a single ended sense amplifier topology that is compatible with the array of single ended cell. Conventionally, sense amplifiers were designed with differential ended topology. This SA topology is usually voltage based in nature owing to their low area footprint and low operational VDD. But delay and current for current mode topology are higher. Thus, generating need for a single ended SA that has low power consumption, smaller area footprint, and faster operation. The convenient sensing topology deemed reliable for single ended SRAM is inverter based.Thus, a single ended switching NMOS based sense amplifier is proposed for 32 nm technology node. It operates in two phases – the pre-charge phase and the evaluation phase. This two-phase functioning for the proposed sense amplifier ensures there is minimal power consumption for the topology when the memory is not executing the read operation. Its pulse-width requirement of 0.32 ns is significantly lower in comparison to its counterparts. While its leakage power is least amongst the different SA topologies at 4 nW. The additional advantage the proposed SA has its lower area footprint of 7.65 µm2 . A bit cell is a small peg in a wide m×n matrix that forms the memory core for data storage. Conventionally, a bit cell is replicated to create the entire array. But, in a typical multimedia application the lower order bits may be more vulnerable to noise than higher order bits. Hence, appreciable performance and minimal image quality degradation can be achieved by using two different bit cells for array formation. A hybrid array configuration using two different 7T bit cells topologies is proposed. The best results are obtained when six dual port and ten single port cells are used to design the array. The static and dynamic power values obtained for the design are 0.29 µW and 23 µW, respectively. These values are 3.5% and 20.7% lower than the static and dynamic power values obtained for memory array designed using only dual port cells. Also, the error tolerance for this partition is approximately 0.015, which is fairly low, making this hybrid array design low power and error resistant.